Voltage storage circuits

ABSTRACT

A voltage storage circuit, for use for example in an analogue-to-digital converter, includes an input switch element connected between an input node (IN) of the circuit and a first plate of a storage capacitor. The other plate of the capacitor is connected to a common terminal 3 of the circuit. A high-impedance amplifier element is connected to the first plate for providing at an output node (OUT) of the circuit an output voltage (V o ) dependent upon the first plate potential (V c ). The amplifier element has an FET input device whose gate electrode is connected to the first plate and whose source and drain electrode potentials are fixed in relation to the first plate potential (V c ). Such a voltage storage circuit avoids charge injection to/from the amplifier element, with consequential charging/discharging of the storage capacitor, which would otherwise result from operation of the amplifier element

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to voltage storage circuits for use, forexample, in analog-to-digital converters for storing an applied analogvalue prior to conversion into its digital equivalent.

2. Description of the Prior Art

FIG. 1 of the accompanying drawings shows a previously-consideredvoltage storage circuit comprising an input switch element 1, a storagecapacitor 2 and a high-impedance unity-gain amplifier element 3.Initially, with the switch element 1 in the closed position, an analoginput voltage V_(i) applied between input terminals of the circuit issupplied to the storage capacitor 2 so that the potential differencebetween the plates of the storage capacitor tracks the input voltageV_(i). At a predetermined moment in time t_(switch) the input switchelement 1 is switched to the open position, with the result that thepotential difference between the capacitor plates immediately prior tosuch switching is stored until such time as the input switch element 1is closed again. During the period in which the switch element is in theopen position the stored voltage is reproduced between output terminalsof the circuit as an output voltage V_(o), the amplifier element 3serving to prevent loading of the storage capacitor by circuitryconnected with the output terminals.

FIG. 2 shows an input portion of the amplifier element 3 in more detail.This input portion includes an FET input transistor 33 having a drainelectrode connected to a positive supply line V_(dd) of the element, asource electrode connected by way of a current source 32 to a negativesupply line V_(ss) of the element, and a gate electrode connected to oneplate (the upper plate in FIG. 1) of the storage capacitor 2. It will beappreciated that the FET input transistor 33 is connected in theso-called source follower configuration.

Further circuitry, not shown in FIG. 2, is normally interposed betweenthe source electrode of the FET input transistor 33 and an output of theelement for buffering the source electrode potential to produce theoutput potential V_(o).

In use of the amplifier element 3 of FIG. 2, the current source 32causes a current to flow in the drain/source channel of the FET inputtransistor 33, with the result that the source electrode potential V_(s)thereof follows the gate electrode potential and hence the storedpotential V_(c) of the upper plate of the storage capacitor 2. Thus, theinput portion of the amplifier element 3 has a voltage gain ofsubstantially unity, although in practice the source electrode potentialV_(s) is always slightly less than the potential V_(c) of the upperplate of the storage capacitor 2.

Because the input portion employs an FET input transistor the gatecurrent of which is very small, the input impedance of the element isvery high. Thus, after the input switch element 1 of the voltage storagecircuit of FIG. 1 has been opened, the storage capacitor is notdischarged to a significant extent by the amplifier element 3.

The amplifier element 3 of FIG. 2 suffers, however, from a disadvantagearising from charge injection into its input portion from the storagecapacitor 2 (or vice versa) when the potential of the upper plate V_(c)of the storage capacitor 2 is changed. Although after the input switchelement 1 has been opened, no such change in the upper plate potentialwill normally result, as explained later in the present specificationthe upper plate potential V_(c) unavoidably changes at the momentt_(switch) of opening of the input switch element 1 due to chargeinjection at that moment by the input switch element 1 itself. Suchcharge injection by the input switch element 1 leads to a small, but athigh precision significant, change in the stored voltage in the storagecapacitor 2 and hence brings about a change in the potential V_(c) ofthe upper plate thereof at the moment the switch element is opened.

The reasons for charge injection at the amplifier element input portion,in response to changes in the upper plate potential of the storagecapacitor 2, will now be explained. As shown in FIG. 2, the FET inputtransistor 33 unavoidably has small parasitic capacitances between itselectrodes, there being a gate-source parasitic capacitance C_(gs)between the gate and source electrodes, a gate-drain parasiticcapacitance C_(gd) between the gate and drain electrodes, and adrain-source parasitic capacitance C_(ds) between the drain and sourceelectrodes. Whenever the potentials of these three electrodes changerelative to one another, charge must flow into or out of the parasiticcapacitances, and it is the combination of these charge flows whichleads to charge injection to/from the amplifier element input portion.

In the FIG. 2 amplifier element, because the input transistor 33 isconnected in the above-mentioned source follower configuration, thegate-source potential thereof is substantially constant, irrespective ofthe upper plate potential V_(c) of the storage capacitor 2, so thatcharge injection due to the gate-source parasitic capacitance C_(gs) cannormally be neglected.

However, the gate potential and the drain-source potential of the inputtransistor 33, being V_(dd) -V_(c) and V_(dd) -V_(s) respectively, arenot constant and vary in dependence upon the upper plate potentialV_(c). Thus, whenever V_(c) is changed, charge must flow into or out ofthe gate-drain parasitic capacitance C_(gd) and the drain-sourceparasitic capacitance C_(ds), in either case causing charge to flow intoor out of the input portion of the amplifier element.

When the input switch element is open, the charge that flows must eithercharge or discharge the storage capacitor 2, depending upon thedirection of flow. Such charge or discharge unavoidably leads to anerror in the stored voltage between the plates of the storage capacitor2.

The effects of the parasitic capacitances of the input portion of theamplifier element are particularly severe when the capacitance of thestorage capacitor 2 is not large relative to the capacitances of theparasitic capacitances themselves, which may be the case for examplewhen it is desired to reduce acquisition time of the voltage storagecircuit.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention there is provided avoltage storage circuit including:

a storage capacitor, one plate of which is connected to an inputterminal of the circuit by way of an input switch element and the otherplate of which is connected to a common terminal of the circuit, aninput signal to be stored being applied between the said input andcommon terminals when the circuit is in use; and

in amplifier element, having an input connected to the said one plateand an output connected to an output terminal of the circuit, forproviding an output signal, between the said output and commonterminals, dependent upon the voltage stored in the said storagecapacitor, which amplifier element includes an electronic input devicehaving a controllable current path provided between respective first andsecond current-path electrodes of the device and also having a controlelectrode to which a potential is applied to control the magnitude ofcurrent in the said current path, the said control electrode beingconnected to the said one plate, and the said first and secondcurrent-path electrodes being connected with potential tracking meanssuch that both the first current-path electrode potential and the secondcurrent-path electrode potential track the control electrode potential,whilst current flows in the said controllable current path, so that therespective potentials of the first and second current-path electrodesare kept substantially fixed in relation to the potential of the saidone plate.

With such a design of amplifier element, the potentials of the controland first and second current-path electrodes of the input device are allin substantially fixed relation to one another and to the one platepotential when the circuit is in use, so that the parasitic capacitancesexisting between those electrodes do not significantly affect operationof the circuit. This avoids charge injection to/from the amplifierelement, with consequential charging/discharging of the storagecapacitor, due to operation of the amplifier element connected to thesaid one plate of the storage capacitor. Thus, error in the storedvoltage as a result of such charging/discharging is eliminated.

Preferably the potential tracking means include a current source,connected to the said first current-path electrode for causing the firstcurrent-path electrode potential to track the control electrodepotential, and active follower means connected operatively between thesaid first and second current-path electrode for causing the secondcurrent-path electrode potential to track the first current-pathelectrode potential.

In such an arrangement the first current-path electrode is caused totrack the one plate potential automatically, so that the active followermeans can be connected operatively between the first and secondcurrent-path electrodes, i.e. exclusively on the output side of theinput device, to achieve the required tracking of the secondcurrent-path electrode.

The said electronic input device is advantageously an FET inputtransistor such that the said control electrode is the gate electrode ofthe FET input transistor, the first current-path electrode is the sourceelectrode of the FET input transistor, the said second current-pathelectrode is the drain electrode of the FET input transistor, and thesaid controllable current path is provided by the drain-source channelof the FET input transistor.

Such an FET input transistor provides the amplifier element with a highinput impedance, so as to avoid discharge of the storage capacitor afterthe input switch element has been opened, the inevitable gate-source,gate-drain, and source-drain parasitic capacitances of the FET inputtransistor not affecting the circuit operation.

When the input device is an FET, the said active follower means maycomprise a cascoding FET transistor connected with its drain-sourcechannel in series with the drain-source channel of the FET inputtransistor so that the source electrode potential of the cascodingtransistor tracks the gate electrode potential thereof and also comprisea bias generator connected operatively between the source electrode ofthe FET input transistor and the gate electrode of the cascadingtransistor for maintaining therebetween a substantially constantpotential difference.

Such a cascoding arrangement is simple but effective, theseries-connection of the cascoding FET transistor with the FET inputtransistor ensuring that the source electrode potential of the cascadingtransistor automatically tracks the gate electrode thereof.

The amplifier element is preferably made up of first and secondsubstantially identical circuit portions, the first portion includingthe said input device and the said active follower means and the secondportion including the said current source.

Such circuit symmetry can provide high stability and predictability inthe operation of the amplifier element, particularly as regards therelationship between the input and output potentials of the amplifierelement, and can be conveniently fabricated.

The said input switch element is preferably an electronic input switchelement, operative in dependence upon the potential at a switchingelectrode thereof, the circuit further including switch driving meansconnected to cause the switching electrode potential to track the inputterminal potential when the element is in its ON condition, therebymaintaining the switching electrode potential substantially fixed inrelation to the input terminal potential, and operable to cause theswitching electrode potential to change, relative to the input terminalpotential, such that the element is changed from its ON condition to itsOFF condition.

In such a circuit the control electrode potential is fixed in relationto the input term potential, so that the amount of charge injected inthe electronic switch element at the moment of switching OFF issubstantially independent of the level of the input signal. Thus, errorin the stored voltage due to such charge injection is substantiallyconstant, or at least linear, for different input signal voltages, andappropriate measures can therefore be taken to compensate for sucherror.

The said switching electrode potential is advantageously derived fromthe said output signal so that this potential can be obtained withoutloading or otherwise affecting the input signal.

Advantageously, the said switch driving means are connected operativelywith the said output terminal and are operable, in dependence upon aswitching signal received thereby, to apply to the said switchingelectrode either an ON potential, for maintaining the said input switchelement in its ON condition, or an OFF potential, for maintaining thesaid input switch element in its OFF condition, the said ON and OFFpotentials being each substantially fixed in relation to the said outputterminal potential but differing from one another by a predeterminedamount.

In this arrangement both the ON and OFF potentials are fixed relative tothe input signal potential so that the charge injection by the inputswitch element is substantially constant irrespective of the inputsignal potential.

The voltage storage circuit may well have respective first and secondbiassing lines connected operatively to the said output terminal so asto be at potentials that are respectively fixed in relation to theoutput terminal potential, the second biassing line potential beingequal to one of the said ON and OFF potentials and the potentialdifference between the said first and second biassing lines beinggreater than or equal to the said predetermined amount. In this case thesaid switch driving means may include a bootstrap capacitor one plate ofwhich is connected to the said switching electrode for providing thesaid switching electrode potential and also include connecting meansconnected with both plates of the bootstrap capacitor and with the saidbiassing lines and switchable, when the switching electrode potential isto be changed from the said one of its ON and OFF potentials to theother of those potentials, from a charging configuration, serving toconnect the said one plate of the bootstrap capacitor to the said secondbiassing line whilst connecting the other plate thereof to the saidfirst biassing line, to a floating configuration serving to isolate thesaid one plate from the second biassing line whilst connecting the saidother plate to the said second biassing line, thereby to cause thepotential at the said one plate to be changed from the second biassingline potential to a potential differing therefrom by the saidpredetermined amount.

In such an arrangement one of the ON and OFF potentials can be outsidethe supply lines of the circuit, if necessary.

Alternatively, the voltage storage circuit may have respective first,second and third biassing lines connected operatively to the said outputterminal so as to be at potentials that are respectively fixed inrelation to the output terminal potential, the third biassing linepotential being equal to one of the said ON and OFF potentials and thepotential difference between the said first and second biassing linesbeing greater than or equal to the said predetermined amount. In thiscase the said switch driving means may include a bootstrap capacitor oneplate of which is connected to the said switching electrode forproviding the said switching electrode potential and also includeconnecting means connected with both plates of the bootstrap capacitorand with the said biassing lines and switchable, when the switchingelectrode potential is to be changed from the said one of its ON and OFFpotentials to the other of those potentials, from a chargingconfiguration, serving to connect the said one plate of the bootstrapcapacitor to the said third biassing line whilst connecting the otherplate thereof to the said first biassing line, to a floatingconfiguration serving to isolate the said one plate from the thirdbiassing line whilst connecting the said other plate to the said secondbiassing line, thereby to cause the potential at the said one plate tobe changed from the third biassing line potential to a potentialdiffering therefrom by the said predetermined amount.

In this example, the required change in the . .control.!..Iadd.switching .Iaddend.electrode potential, from the said outputterminal potential when the switch element is in one of its ON and OFFconditions to a potential differing from the output terminal potentialby the said predetermined amount when the switch element is in the otherof its ON and OFF conditions, can be achieved using internal biasinglines whose potentials are not suitable for directly providing the ONand OFF potentials and/or whose potentials differ from the outputterminal potential by less than the predetermined amount.

Preferably the said electronic input switch element is a MOSFETtransistor in which case one of the said ON and OFF potentials can besubstantially the same as the said output terminal potential. Forexample, if the MOSFET transistor is an n-channel enhancement typeMOSFET, the OFF potential can be substantially the same as the outputterminal potential. With such a MOSFET transistor as the electronicswitch element the generation of suitable ON and OFF potentials can bedesirably simple, particularly in the case of the said one of the ON andOFF potentials that can be obtained by simply applying the outputterminal potential directly to the . .control.!. .Iadd.switching.Iaddend.electrode.

Preferably the voltage storage circuit is formed on a single substrate,and the said input switch element and the said input device of theamplifier element are located within one or more wells of theconductivity type opposite to that of the surrounding material of saidsubstrate, there being means for causing the or each well potential totrack the potential of the said one plate. By controlling the potentialof the well in this way, parasitic capacitances (including the switchelement capacitance and any interconnect capacitance) of the circuit canbe bootstrapped out. The well may, for example, be connectedelectrically to the said output terminal of the circuit. This permitsthe well potential to track the output terminal potential.

The said storage capacitor may also located within such a well tobootstrap parasitic capacitances associated therewith.

Advantageously, one or more conductive shields extend over the area ofthe or each well, and there are means for causing the or each shieldpotential to track the potential of the said one plate. This assists ineliminating residual parasitic capacitance effects. In such a case, thesaid conductive shield may also usefully be connected electrically tothe said output terminal of the circuit so that the shield potentialtracks the output terminal potential.

When the amplifier element of the voltage storage circuit comprises twosubstantially identical circuit portions as described above, the saidfirst portion of the amplifier element is preferably located within thesaid one or more wells, and the said second portion of the amplifierelement is formed within one or more further wells, each of theconductivity type opposite to that of the surrounding areas of thesubstrate, the or each further well potential being substantially fixedin relation to the potential of a supply line of the circuit.

The voltage storage circuit preferably further includes input potentialmaintaining means, interposed between the said input terminal and theinput side of the said input switch element, for maintaining theinput-side potential of the input switch element, after the element ischanged to the OFF condition, substantially fixed in relation to thepotential of the said one plate of the storage capacitor.

This can prevent the input switch element from becoming turned ONinadvertently should the input signal potential change sufficientlyrelative to the . .control.!. .Iadd.switching .Iaddend.electrodepotential after the element has been turned OFF.

The said input potential maintaining means may comprise a further switchelement connected in series with the said input switch element andoperable, after the said input switch element has been changed to theOFF condition, to isolate the input side of that element from the saidinput terminal. In this way, variation in the input signal potentialafter opening of the further switch element does not affect the inputside potential of the input switch element.

The said input potential maintaining means may further comprise anauxiliary capacitor connected between the input side of the said inputswitch element and the said other plate of the said storage capacitorand/or a feedback switch element connected between the said amplifierelement and the input side of the said input switch element andoperable, while the input side of that element is so isolated, to applythereto a potential derived from the potential of the said one plate ofthe storage capacitor.

The gain of the said amplifier element is preferably substantiallyunity. In this case the . .control.!. .Iadd.switching .Iaddend.electrodepotential and the well potential(s) can conveniently be "bootstrapped"to the output terminal potential because, when the amplifier element hasa gain of substantial unity, the buffered output terminal potential issubstantially equal to the one plate potential/input signal potential.Thus, the required . .control.!. .Iadd.switching .Iaddend.electrodepotential can be derived from the buffered output signal withoutaffecting the input signal.

Such a voltage storage circuit (the amplifier element of which has unitygain) as described above may usefully be included in voltage summationcircuitry which also includes:

first, second and third input nodes to which first, second and thirdpotentials are applied when the circuitry is in use;

an output node connected with the output terminal of the voltage storagecircuit; and

switching means connected with the said input nodes and with the saidvoltage storage circuit and switchable, after the input switch elementof the voltage storage circuit has been changed to the OFF condition,from an input configuration to an output configuration, said inputconfiguration serving to connect the said first and second input nodesto the said input and common terminals respectively of the voltagestorage circuit, thereby to permit storage of the potential differencebetween the said first and second potentials in the storage capacitor ofthe voltage storage circuit, and said output configuration serving toconnect the common terminal of the voltage storage circuit to the saidthird input node, thereby to produce at the said output node an outputpotential which is substantially equal to the sum of the third potentialand the stored difference between the first and second potentials.

Such voltage summation circuitry is capable of very high precisionvoltage summation, the accuracy being essentially limited only by theeffectiveness with which the effects of parasitic capacitances in thevoltage storage circuit can be eliminated. When, in each voltage storagecircuit, the various parasitic capacitances of the circuit (the switchelement capacitance, the amplifier element input capacitance and anyinterconnect capacitance) are bootstrapped out using the techniquesindicated above, substantially the only limit on cancellation ofparasitic capacitance effects arises from gain error of the amplifierelements. This gain error can be reduced to very low levels by adoptingsuitable designs of the amplifier element.

First and second voltage storage circuits, each as described above andeach having unity-gain amplifier elements, may be advantageouslyincluded in voltage summation circuitry which also includes:

first, second, third, fourth, fifth and sixth input nodes, a first pairof input voltages being applied to the said first and second inputnodes, and a second pair of input voltages being applied to the saidthird and fourth input nodes, and a third pair of input voltages beingapplied to the said fifth and sixth input nodes, when the circuitry isin use;

first and second output nodes connected with the respective outputterminals of the said first and second voltage storage circuits; and

switching means connected with the said input nodes and with the saidvoltage storage circuits and switchable, after the respective inputswitch elements of the first and second voltage storage circuits havebeen changed to the OFF condition, from an input configuration to anoutput configuration, said input configuration serving to connect thesaid first and second input nodes to the said input and common terminalsrespectively of the said first voltage storage circuit, and also toconnect the said third and fourth input nodes to the said input andcommon terminals respectively of the said second voltage storagecircuit, thereby to permit storage, in the said storage capacitor of thefirst voltage storage circuit, of a first potential difference betweenthe two input voltages of the said first pair and to permit storage, inthe said storage capacitor of the second voltage storage circuit, of asecond potential difference between the two input voltages of the saidsecond pair, and said output configuration serving to connect therespective common terminals of the first and second voltage storagecircuits to the fifth and sixth input nodes respectively, thereby toproduce between the said first and second output nodes a pair of outputvoltages the potential difference between which is substantially equalto the sum of the potential difference between the two input voltages ofthe said third pair and the difference between the stored first andsecond potential differences.

By virtue of the back-to-back connection of the two voltage storagecircuits the individual (fixed) amounts of charge injected by therespective switch elements thereof at the moment they are turned OFF arethe same for each circuit and hence effectively cancel one another outbearing in mind the differential nature of the input and output of thecircuitry.

First and second voltage storage circuits, each as described above andeach having unity-gain amplifier elements, may in another preferredexample be included in voltage doubling circuitry which also includes:

first and second input nodes between which an input voltage to bedoubled is applied when the circuitry is in use;

first and second output nodes connected respectively with the respectiveoutput terminals of the first and second voltage storage circuits; and

switching means connected with the said input nodes and with the saidvoltage storage circuits and switchable, after the respective inputswitch elements of the first and second voltage storage circuits havebeen changed to the OFF condition, from an input configuration to anoutput configuration, said input configuration serving to connect thesaid first input node to both the said input terminal of the said firstvoltage storage circuit and the said common terminal of the said secondvoltage storage circuit, and also to connect the said second input nodeto both the said input terminal of the said second voltage storagecircuit and the said common terminal of the said first voltage storagecircuit, thereby to cause each of the respective storage capacitors ofthe said voltage storage circuits to be charged to the said inputvoltage, and said output configuration serving to connect the respectivecommon terminals of the first and second voltage storage circuitstogether so that the said storage capacitors are connected in serieswith one another between the . .said first and second output nodes,thereby to produce between those.!. .Iadd.respective amplifier-elementinputs of said first and second voltage storage circuits, thereby toproduce between the first and second .Iaddend.output nodes an outputvoltage which is substantially double the said input voltage.

Again, the back-to-back connection of the two voltage storage circuitsaffords cancellation of the charge injected by the input switchelements, so that the doubled voltage is highly accurate. The circuitryhas a much improved speed/power/noise trade-off, perhaps up to ten timesbetter, than comparable prior proposals.

Such voltage doubling circuitry has a particularly advantageousapplication in analog-to-digital converters that carry out voltagedoubling operations in the course of their conversion operations. Such aconverter may incorporate a voltage conversion stage including:

voltage doubling circuitry as described above;

comparator means connected for receiving a working voltage equal to orderived from the said input voltage and also connected for receiving acomparison potential and operable to perform a comparison between thatworking voltage and the said comparison potential and to provide digitaldata indicative of the result of the comparison; and

voltage adjustment means connected between the respective commonterminals of the said first and second voltage storage circuits andoperable, after the said switching means have been switched from thesaid input configuration to the said output configuration, to applybetween those terminals an offset voltage having a value selected, bythe said digital data, from a plurality of preset possible values,thereby to produce between the said output nodes an analogue conversionvoltage which differs from double the said input voltage by the selectedoffset voltage.

In such a conversion stage, by virtue of the use of high-precisionvoltage doubling circuitry as described above, the analogue conversionvoltage can be derived with desirably high precision from the inputvoltage without the use of complex switching arrangements tointerconnect the two storage capacitors. This analogue conversionvoltage can be offset, from double the input voltage, by one of a numberof preselected offset voltages selected in dependence upon the inputvoltage magnitude, as is required for example in analogue-to-digitalconverters of the "three-state-logic" kind. The said voltage adjustmentmeans are connected between the respective common terminals of the saidfirst and second voltage storage circuits and are operable to applybetween those terminals the said offset voltage. In this way, since thevoltage adjustment means are connected in series with the two storagecapacitors so as to cause a potential difference equal to the selectedoffset voltage to exist between the respective said other plates of thecapacitors, and each storage capacitor has a potential differencebetween its respective plates equal to the input voltage, the requiredoffset of the analogue conversion voltage from double the input voltageis achieved simply and accurately, without employing complex andinaccurate analogue voltage adders.

Preferably the said comparator means perform the said comparison whilstthe switching means of the voltage storage circuits are in the saidinput configuration, providing high-speed operation.

In one preferred example, the said comparator means are connected to thesaid first and second input nodes, so that the said input voltage is thesaid working voltage, and provide first such digital data if the saidinput voltage is less than or equal to minus the said comparisonpotential, and provide second such digital data if the said comparisonpotential is less than or equal to the said input voltage, and providethird such digital data in all other cases, and wherein the offsetvoltage selected by the said second digital data is -V_(ref), where+V_(ref) is the offset voltage selected by the said first digital data,and the offset voltage selected by the said third digital data is zero;the said comparison potential being substantially equal to V_(ref) /4.

By virtue of the immunity of the conversion algorithm embodied in such aconversion stage to missing code errors that would otherwise arise fromoffset voltage of the comparator means, the full benefit of theimprovement in the precision of the voltage conversion operationperformed by the stage is obtained in terms of overall conversionaccuracy.

One particularly-advantageous such analogue-to-digital convertercomprises:

a series of N stages, each being a voltage conversion stage as describedabove, an analogue voltage to be digitised being applied between thesaid first and second input nodes of the first stage of the series, andthe said first and second input nodes of each successive stage beingconnected to the said first and second output nodes respectively of theimmediately-preceding stage;

control means operable to cause the switching means of each of the saidstages in succession to be switched from the said input configuration tothe said output configuration, such switching being controlled to occurin each of the stages, except for the first stage, at a time when theswitching means of the immediately-preceding stage is in the outputconfiguration so that prior to such switching the stage being switchedreceives as its input voltage the analogue conversion voltage producedby that immediately-preceding stage and so produces its analogueconversion voltage in dependence thereupon after such switching; and

data processing means connected for receiving the said digital dataprovided by the said N stages and operative to derive therefrom adigital output word, comprising N+1 bits, representative of the appliedanalogue voltage.

Such an analogue-to-digital converter can operate very quickly,producing one full N+1 bit digital output word per clock period.

Preferably, such an analogue-to-digital converter is operativealternately in first and second clock phases, and the said control meansoperate in the said first clock phase to maintain the respectiveswitching means of the odd-numbered stages of the series in the inputconfiguration whilst maintaining the respective switching means of theeven-numbered stages in the said output configuration but operate in thesaid second clock phase to maintain the respective switching means ofthe even-numbered stages in the said input configuration whilstmaintaining the respective switching means of the odd-numbered stages inthe output configuration.

This arrangement permits the converter to operate at the above-mentionedhigh speed while keeping the control of the stages desirably simple.

Advantageously, for at least one pair of adjacent stages of the series,the respective storage capacitors of the said first and second voltagestorage circuits in the second stage of the pair are smaller incapacitance than the comparable storage capacitors in the first stage ofthe pair, the storage capacitance ratio of the two stages of one or eachsuch pair being preferably approximately 2:1. This can assist inreducing power consumption of the converter.

For at least one pair of adjacent stages of the series, the respectiveamplifier element input devices of the said first and second voltagestorage circuits in the second stage of the pair are preferably smallerin width than the comparable input devices in the first stage of thepair, the input device width ratio of the two stages of one or each suchpair being advantageously approximately 2:1, again to reduce powerconsumption.

Furthermore, for at least one pair of adjacent stages of the series, therespective currents in the controllable current paths of the amplifierelement input devices of the said first and second voltage storagecircuits in the second stage of the pair may be smaller than thecomparable currents in the first stage of the pair, the current ratio ofthe two stages of one or each such pair being preferably approximately2:1, again to assist in reducing power consumption.

Advantageously, in each of the second to nth stages of the converter,where 2≦n≦N, each of the respective storage capacitors of the said firstand second voltage storage circuits of the stage has a capacitance thatis reduced, relative to the capacitance of the comparable storagecapacitor of the immediately-preceding stage, by a first scaling factorthat is constant throughout those second to nth stages. Scaling thecapacitance by a constant scaling factor in this way helps to reducepower consumption of the converter and to reduce the amount of chip arearequired to make the converter.

The said first scaling factor is preferably 2. This value of scalingfactor is optimal in terms of reduced power consumption.

Advantageously, in each of the second to nth stages of the converter,where 2≦n≦N, the amplifier element input device of each voltage storagecircuit of the stage is of a channel width that is reduced, relative tothe channel width of the comparable amplifier element input device ofthe immediately-preceding stage, by a second scaling factor that isconstant throughout those second to nth stages.

Such scaling by a constant factor for a number of successive stages canalso contribute to reducing the power consumption of the converter andthe chip area occupied thereby.

The said second scaling factor is preferably also 2. This results inoptimal power consumption reduction.

Advantageously also, in each of the second to nth stages of theconverter, where 2≦n≦N, the current in each of the said controllablecurrent paths of the amplifier element input devices of the stage iscontrolled to be reduced, relative to the current in the comparablecontrollable current path of the immediately-preceding stage, by a thirdscaling factor that is constant throughout those second to nth stages.

Such scaling can further contribute to a reduction in the powerconsumption of the converter.

The said third scaling factor is preferably also 2. This value isoptimal in terms of power consumption reduction.

In another preferred embodiment, for at least one pair of adjacentstages of the series, at least one of the said preset possible values ofthe offset voltage in the second stage of the pair is adjustedfractionally as compared with the corresponding preset possible value ofthe offset voltage in the first stage of the pair.

Such a fractional adjustment can be used to correct for gain errors inthe amplifier elements used in each stage, and hence can maintainhigh-precision operation of the overall converter despite imperfectionsin those amplifier elements.

Alternatively, or in addition, the said data processing means may beoperable to fractionally adjust the digital data provided by therespective comparator means of successive stages of the series so as tofacilitate correction of voltage conversion errors in those successivestage.

Another advantageous analogue-to-digital converter comprises:

first and second stages, each being a voltage conversion stage asdescribed above, connected together such that the said first and secondoutput nodes of the fist stage are connected to the said first andsecond input nodes respectively of the second stage and the said firstand second output nodes of the said second stage are connected to thesaid first and second input nodes respectively of the first such stage,an analogue voltage to be digitised being applied, at the start of aniterative conversion operation of the converter, between the said firstand second input nodes of the said first stage;

control means operable to cause the switching means of the first andsecond stages to be switched alternately, starting with the first stage,from the said input configuration to the said output configuration, suchswitching being controlled to occur in one stage at a time when theswitching means of the other stage are in the output configuration sothat prior to such switching the one stage being switched receives asits input voltage the analogue conversion voltage produced by the otherstage and so produces its analogue conversion voltage in dependencethereupon after such switching; and

data processing means connected for receiving the said digital dataprovided alternately by the first and stages during the course of thesaid iterative conversion operation and operative to derive therefrom adigital output word representative of the applied analogue voltage.

In such an analogue-to-digital converter only two stages are required toperform a conversion operation, resulting in a desirably compact andsimple design

According to a second aspect of the present invention there is providedan analogue-to-digital converter, operable alternately in first andsecond clock phases, including:

first and second input nodes between which an analogue input voltage tobe digitised can be applied when the converter is in use;

first and second voltage storage circuits, each including respectivefirst and second storage capacitors and a unity-gain amplifier elementhaving respective input and output terminals, which element includes anelectronic input device having a controllable current path providedbetween respective first and second current-path electrodes of thedevice and also having a control electrode to which a potential isapplied to control the magnitude of current in the said current path,the said control electrode being connected to the said input terminal ofthe amplifier element, and the said first and second current-pathelectrodes being connected with potential tracking means such that boththe first current-path electrode potential and the second current-pathelectrode potential track the control electrode potential, whilstcurrent flows in the said controllable current path, so that therespective potentials of the first and second current-path electrodesare kept substantially fixed in relation to the potential of the saidinput terminal;

input sampling means operable during an initial one of the clock phasesto connect the said input terminal of the first voltage storage circuitto the said first input node and to connect the said input terminal ofthe second voltage storage circuit to the said second input node;

first and second output nodes connected respectively with the amplifierelement output terminals of the said first and second voltage storagecircuits;

comparator means connected to the said first and second output nodes andalso connected for receiving a comparison potential and operable in eachclock phase to perform a comparison between the potential differencebetween the first and second output nodes and the said comparisonpotential and to provide digital data indicative of the result of thecomparison;

voltage adjustment means having a pair of connection terminals andoperable in each clock phase to apply between those terminals an offsetvoltage having a value selected, by the said digital data provided bythe said comparator means in the immediately-preceding clock phase, froma plurality of preset possible values;

switching means operable in the first clock phase to connect the twofirst storage capacitors and the said connection terminals in seriesbetween the respective input terminals of the amplifier elements, whilstconnecting the said second storage capacitors in parallel with oneanother between the first and second output nodes, and operable in thesecond clock phase to connect the two second storage capacitors and thesaid connection terminals in series between the respective inputterminals of the amplifier elements, whilst connecting the said firststorage capacitors in parallel with one another between the first andsecond output nodes; and

data processing means connected for receiving the said digital dataprovided by the said comparator means over a predetermined number of thesaid clock phases and operative to derive therefrom a digital outputword representative of the applied analogue input voltage.

Such an analogue-to-digital converter requires only one stage to performa conversion operation, resulting in an especially compact design.

According to a third aspect of the present invention there is providedan analog-to-digital converter including a plurality of mutually-similarvoltage conversion stages connected in series so that the output of onestage provides an input to the next stage, each stage including astorage capacitor selectively connectible to the input of the stage forstoring an input voltage of the stage and also including an amplifierelement selectively connectible between the storage capacitor and theoutput of the stage for delivering an output voltage of the stage whichis dependent on the stored input voltage, wherein in at least one stage,other than the first stage, of the series the storage capacitorcapacitance is smaller than the storage capacitor capacitance of theimmediately-preceding stage and/or the width of an input transistor ofthe amplifier element is smaller than the width of the input transistorof the amplifier element of the immediately-preceding stage.

Such an analogue-to-digital converter, employing a series of "scaled"voltage conversion stages, can achieve an improved overall noise/powerconsumption tradeoff. The factor (scaling factor) by which the storagecapacitor capacitance and/or input transistor width is scaled from onestage to the next is preferably close to 2. Scaling may be stopped afterthe first few stages, for example the first six stages may be scaled onefrom the next and then the remaining stages can be constant size.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (PRIOR ART), discussed hereinbefore, shows a circuit diagram of apreviously-considered voltage storage circuit;

FIG. 2 (PRIOR ART), also discussed hereinbefore, shows in more detail anamplifier element included in the FIG. 1 circuit;

FIG. 3 shows a circuit diagram of a voltage storage circuit embodyingthe aforesaid first aspect of the present invention;

FIG. 4 shows one design of an amplifier element included in the FIG. 3circuit;

FIG. 5 shows another design of amplifier element for use in the FIG. 3circuit;

FIG. 6 shows in more detail an input witch element included in the FIG.3 circuit;

FIG. 7 shows yet another design of amplifier element, together with anexample of switch driving means, for use in the FIG. 3 circuit;

FIGS. 8(A) and 8(B) show respective plan and cross-sectional viewsillustrating one possible layout of the circuit of FIG. 3 on anintegrated circuit substrate;

FIGS. 9(A) and 9(B) show respective plan and cross-sectional viewsillustrating another possible layout of the circuit of FIG. 3 on anintegrated circuit substrate;

FIG. 10 shows a circuit diagram of voltage summation circuitry employinga voltage storage circuit as shown in FIG. 3;

FIG. 11 shows a circuit diagram of voltage doubling circuitry employingtwo voltage storage circuits as shown in FIG. 3;

FIG. 12 shows a circuit diagram of parts of an analogue-to-digitalconverter having a plurality of conversion stages each based upon thevoltage doubling circuitry of FIG. 11;

FIG. 13 shows a circuit diagram of parts of an analogue-to-digitalconverter, having a single conversion stage, embodying the aforesaidsecond aspect of the present invention;

FIG. 14 is a schematic diagram of parts of the converter of FIG. 12, forillustrating advantages of scaling the stages in the FIG. 12 converterone from the next by a scaling factor;

FIG. 15 is a graph illustrating, in the case of a converter as shown inFIG. 12 having 16 stages, the relationship between total currentconsumption of the converter and the scaling factor, and therelationship between total noise in the converter and the scalingfactor; and

FIG. 16 is a schematic diagram illustrating one example of the layout ofthe FIG. 12 converter on a chip.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The voltage storage circuit of FIG. 3 includes an electronic switchelement 1, preferably an MOSFET transistor, a storage capacitor 2, aunity-gain buffer 3, and a bootstrapped switch driving device 4,5connected between an output terminal circuit and the gate electrode(control electrode) of the MOSFET 1.

FIG. 4 shows a first example of the construction of the amplifierelement 3 in the FIG. 3 circuit. The element 3 comprises two basicportions, namely a cascoded source follower 31 and a current source 32.

The cascoded source follower 31 comprises an n-channel MOSFET inputtransistor 33 whose gate electrode is connected to one plate (the upperplate in FIG. 3) of the storage capacitor 2. The drain-source channel ofthe input transistor 33 is connected in series with the drain-sourcechannel of a further n-channel MOSFET transistor, which will be referredto hereinafter as a cascoding transistor 34. The drain electrode of thecascoding transistor 34 is connected to a positive supply line V_(dd) ofthe circuit, whilst the source electrode of the input transistor 33 isconnected to an output terminal OUT of the circuit.

Also in the cascoded source follower 31, a bias generator 35 isconnected between the source electrode of the input transistor 33 andthe gate electrode of the coding transistor 34. This bias generatorserves to maintain a substantially constant potential difference betweenthe gate electrode of the cascode transistor and the source electrode ofthe input transistor 33, irrespective of variation of the sourceelectrode potential.

The current source 32 is constituted substantially identically to thecascoded source follower 31 and comprises two n-channel MOSFETtransistors 36 and 37 (corresponding respectively to the transistors 33and 34 of the cascoded source follower 31), connected in series betweenthe output terminal OUT of the circuit and a negative supply line V_(ss)of the circuit, an associated bias generator 38 (corresponding to thebias generator 35 in the cascoded source follower 31) which serves tomaintain a substantially constant potential difference between the gateelectrode of the transistor 37 and the source electrode of thetransistor 36. In this case, the source electrode of the transistor 36is connected directly to the negative supply line V_(ss), so that thegate electrode potential of the transistor 37 is fixed in relation tothe negative supply line. The current source 32 has a bias input BIASconnected to the gate electrode of the transistor 36. A bias potentialcan be applied to the bias input of the current source 32 forcontrolling operation of the element, as will be described hereinafter.

Since the current source 32 is connected in series with the cascodedsource follower 31, it serves to complete a current path between thepositive and negative supply lines V_(dd) and V_(ss).

In operation of the amplifier element of FIG. 4, the current source isoperable to cause a substantially constant current to pass through theabove-mentioned current path and hence through each of the transistors33 and 34 of the cascoded source follower 31. This causes the sourceelectrode potential of the input transistor 33 to track the gateelectrode potential thereof such that the output terminal potentialV_(o) follows the potential V_(c) of the upper plate of the storagecapacitor 2. Thus, the voltage gain of the element is substantiallyunity.

Similarly, the source electrode potential of the cascoding transistor 34is caused to track the gate electrode potential thereof, which potentialis in turn maintained substantially fixed in relation to the sourceelectrode potential of the input transistor 33 by the bias generator 35.Accordingly, the drain electrode potential of the input transistor 33tracks the source electrode potential thereof and hence also tracks thepotential V_(c) of the upper plate of the storage capacitor 2.

As will be apparent, irrespective of the upper plate potential V_(c) ofthe storage capacitor 2, the source and drain electrode potentials ofthe input transistor 33 are each substantially fixed in relation to oneanother and to the gate electrode potential of that input transistor.Thus, the gate-source, gate-drain and drain-source parasiticcapacitances C_(gs), C_(gd), C_(ds) are not charged or discharged as theupper plate potential V_(c) of the storage capacitor 2 varies, and thusthese parasitic capacitances have substantially no effect on the voltagestored in the storage capacitor 2.

Because the input transistor 3 is an FET input transistor, the gatecurrent is substantially zero, so that the charge stored in the storagecapacitor is not diminished significantly by operation of the amplifierelement 3 after the input switch element 1 has been opened.

In the FIG. 4 amplifier element, the actual output terminal potential isnot exactly equal to the upper plate potential V_(c), but is reducedslightly in accordance with the ON gate-source differential voltage ofthe transistor 33, as follows:

    V.sub.O =V.sub.c -(V.sub.T +V.sub.DSAT)

where V_(T) is the threshold voltage of the input transistor 33 andV_(DSAT) is the saturation voltage of the input transistor 33.

As will be apparent from FIG. 4, the cascoded source follower 31 and thecurrent source 32 are constructed substantially identically to oneanother. Thus, the counterpart of the input transistor 33 of thecascaded source follower 31 is the transistor 36 in the current source32, to which transistor 36 the above-mentioned bias potential isapplied. Because the same current flows through the respectivedrain-source channels of the transistors 33 and 36, and thesetransistors are of identical dimensions, the gate-source potential ofthe transistor 33 can be controlled by adjusting the gate-sourcepotential of the transistor 36 in the current source 32. Thisgate-source potential of the transistor 36 is equal to the differencebetween the bias potential and the negative supply line potential sothat by applying a suitable constant bias potential to the bias terminalthe difference between the output terminal potential V_(o) and the upperplate potential V_(c) of the storage capacitor 2 can be set to adesirably small constant level.

In the FIG. 4 amplifier element, the transistors 33, 34, 36 and 37 canbe of the depletion or enhancement type.

FIG. 5 shows a more sophisticated example of the construction of theamplifier element 3, employing depletion-type n-channel MOSFETtransistors to provide high speed operation. In the FIG. 5 example, theamplifier element again comprises a cascoded source follower 31 and acurrent source 32, and the FET input transistor 33 in the cascodedsource follower 31 is again connected in the cascoded source followerconfiguration previously described with reference to FIG. 4, the gateelectrode of the transistor 33 being connected to receive the upperplate potential V_(c) of the storage capacitor 2, the source electrodeof the transistor 33 being connected to the output terminal OUT of thecircuit and the drain electrode of the transistor 33 being connected byway of first and second cascoding transistors 341 and 342 to thepositive supply line V_(dd) of the circuit.

In this case, the cascode bias generator 35 comprises threeseries-connected transistors 351, 352 and 353 connected for applyingsuitable bias potentials to the respective gate electrodes of the firstand second cascoding transistors 341 and 342, so that the respectivegate electrodes of the cascading transistors 341 and 342 are eachmaintained at potentials substantially fixed in relation to the sourceelectrode potential of the input transistor 33.

The current source 32 of the FIG. 5 amplifier element is constitutedidentically to the cascoded source follower 31 thereof and includes,connected between the source electrode of the input transistor . .31.!..Iadd.33 .Iaddend.and the negative supply line V_(ss), threeseries-connected transistors 36, 371 and 372 (corresponding respectivelyto the transistors 33, 341 and 342 of the cascoded source follower 31).In this case the gate electrode potential of the transistor 36(equivalent to the bias potential applied to the bias input in the FIG.4 amplifier element) is provided by the negative supply line V_(ss),while the respective gate electrode potentials of the transistors 371and 372 are provided by a bias generator 38 (constructed identically tothe bias generator 35 in the cascoded source generator 31) comprisingthree series-connected transistors 381 to 383. It will be seen that thebias generators 35 and 38 are connected in series with one anotherbetween the positive and negative supply lines so as to complete afurther current path therebetween.

In the FIG. 5 amplifier element, because the gate electrode of thetransistor 36 in the current source 32 is connected directly to thenegative supply line V_(ss), the gate and source potentials of thetransistor 36 are equal to one another. Since the same drain-sourcecurrent flows through the input transistor 33 as through its counterparttransistor 36 in the current source 32, and the cascoded source follower31 and the current source 32 are of substantially identicalconstruction, it follows that the gate and source potentials of theinput transistor 33 in the cascoded source follower 31 will also besubstantially equal to one another in potential. Thus, the voltage gainof the FIG. 5 amplifier element is closer to unity (approximately0.9995) than is the case with the FIG. 4 amplifier element. As comparedwith the FIG. 4 amplifier, the FIG. S amplifier element is also capableof fast operation. In other respects, however, the operation of the FIG.5 element is substantially identical to that of the FIG. 4 amplifierelement.

Returning now to FIG. 3, the bootstrapped switch driving devicecomprises potential generating circuitry 4 having an input connected tothe output terminal of the circuit and operable to provide at respectiveoutputs thereof potentials V_(high) and V_(low) (V_(high) >V_(low)) eachof which has a constant offset from the output terminal potential. Thesetwo potentials must be at suitable levels to apply to the gate electrodeof the MOSFET 1 in order to maintain it in its ON and OFF conditions.

The two potentials V_(high) and V_(low) are applied as inputs to aselector element 5 which also receives a switching signal CK. The outputof the selector circuit 5 is connected to the gate electrode of theMOSFET switch element 1 for controlling the potential thereof. Theselector element 5 switches the gate electrode potential between the twopotentials V_(high) and V_(low) in dependence upon the switching signalCK. This signal CK may be a logic signal provided by digital logiccircuitry controlling operation of the voltage storage circuit.

In order to avoid unpredictable charge injection by the MOSFET inputswitch element 1 into the storage capacitor 2 when the input switchelement is turned OFF, the control potential applied to the gateelectrode of the MOSFET must be substantially fixed in relation to theinput terminal potential at least when the MOSFET is to be ON, as willnow be explained with reference to FIG. 6.

FIG. 6 shows the input switch element 1, in this example an n-channelenhancement type MOSFET, in detail. The MOSFET 1 has a source electrodeproviding an input terminal IN of the switch element, a drain electrodeproviding an output terminal OUT of the switch element, and a gateelectrode connected to be switched alternatively between the twoabove-mentioned control potentials V_(high) and V_(low). Thedrain-source channel of the transistor is non-conducting when thegate-channel potential thereof is zero (or negative) so that when theapplied control potential is V_(low) (≦V_(o)) the output terminal of theswitch element is isolated from the input terminal thereof, theoff-resistance (R_(off)) of the switch element in this condition beingtypically more than 10,000 MΩ. When the gate potential is changed toV_(high) (>V_(o)) the drain-source channel is brought into conduction,the on-resistance (R_(on)) of the switch element in this condition beingof the order of 10s or 100s of ohms.

In an analog-to-digital converter employing a voltage storage circuitsuch as that shown in FIG. 3 the operation of the switch element 1 isnormally required to be controlled by digital logic circuitry of theconverter and, partly for this reason, in prior proposals fixed digitallogic potentials (for example 0 and +V_(DD) volts) were conventionallyapplied to the gate to control the switching of the element.

However, a problem arises when such digital logic potentials are used aswill now be explained.

The MOSFET switch element 1 of FIG. 6 unavoidably has a parasiticgate-channel capacitance C_(gc) between its gate electrode and itsdrain-source channel. This parasitic capacitance has a first componentdue to physical overlap between the gate and the channel of the FET, anda second component associated with charge stored in the channel when theFET is in the ON condition. It is found that this second component vaneswith the channel potential (i.e. with the potential V_(i) of the signalbeing switched) but in an unpredictable manner.

The gate-channel capacitance gives rise to charge injection from thegate to the channel at the moment of switching t_(switch), which in tangives rise to an error in the stored voltage. Charge injection due tothe above-mentioned first component of the gate-channel capacitancedepends essentially on the change in gate voltage ΔV_(G) at t_(switch)(eg. O-V_(DD) =-V_(DD)) and so is substantially independent of thechannel potential V_(i) at t_(switch). Charge injection due to thesecond component of the gate-channel capacitance is, however, influencedby the input signal potential V_(i) relative to the gate potential atthe moment of switching, leading to the above-mentioned error in thestored voltage and for non-linearity in the operation of the voltagestorage circuit

It is not readily practical to compensate for such charge injection, forexample by coupling an inverted version of the gate signal through amall adjustable capacitor, because the effect of the above-mentionedsecond component of the gate-channel capacitance is not sufficientlypredictable.

The effects of charge injection at the moment of switching t_(switch)prior proposals employing fixed control potentials, such as digitallogic potentials, are particularly significant in the case where it isdesired to employ a storage capacitor having a small capacitance toreduce the acquisition time of the circuit.

In the bootstrapped switch driving device 4, 5 of FIG. 3, however, atleast the control potential applied to the switch element 1 to maintainit in the ON condition is fixed relative to the input terminal potentialV_(i) so that the amount of charge injected by the element 1 when it isswitched OFF is substantially constant irrespective of the inputterminal potential. Because this charge injection is constant, it leadsto a constant error in the stored voltage, which can be readilycompensated for.

Incidentally, in some cases it may be possible for the control potentialapplied to the switch element 1 when it is to be maintained in the OFF(as opposed to the ON) condition to be fixed, rather than variable withthe input potential V_(i) as in FIG. 3. This is because theabove-mentioned first component of the gate-channel parasiticcapacitance C_(gc) is linear.

The potentials V_(high) and V_(low) required depend on the type andthreshold voltage of the MOSFET used in the MOSFET 1. This switchelement can be of the enhancement or depletion type and can be ofn-channel or p-channel. For an n-type channel MOSFET, V_(high) will beapplied to the gate electrode to turn ON the MOSFET (i.e. V_(high) isthe ON potential and V_(low) will be applied to turn it OFF (i.e.V_(low) is the OFF potential, whereas for a p-channel MOSFET V_(high)will be applied to the gate electrode to turn OFF the MOSFET (i.e.V_(high) is the OFF potential) and V_(low) will be applied to turn it ON(i.e. V_(high) is the ON potential).

In the case of an n-channel MOSFET having a threshold voltage V_(T), forlow on-resistance

    V.sub.high -V.sub.i ≧V.sub.T +V.sub.on

where V_(on) is a predetermined potential difference. Similarly, forhigh off-resistance

    V.sub.low -V.sub.i <V.sub.T -V.sub.off,

where V_(off) is also a predetermined potential difference.

The difference between the ON and OFF potentials is thus V_(on)+V_(off), which must be at least several hundred mV.

It may be possible to use the output terminal potential V_(o) directlyto provide one of the two potentials V_(high) and V_(low). For example,in the case in which the MOSFET switch element 1 is an n-channeldepletion type switch element V_(high) can simply be V_(o) ; likewise,in the case in which the MOSFET switch element 1 is an n-channel cementtype switch element, V_(low) can be the output terminal potential V_(o).

In the FIG. 3 voltage storage circuit, the potential generatingcircuitry 4 is shown interposed between the output terminal and theselector circuit 5. However, this circuitry 4 may in some cases beomitted if the required potentials V_(high) and V_(low) are alreadyavailable on existing internal biasing lines of the circuit, inparticular on internal biasing lines of the amplifier element 3.Alternatively, as will be described later in more detail with referenceto FIG. . .9.!. .Iadd.7.Iaddend., the required potentials V_(high) andV_(low) may be derived from internal biassing line potentials that arenot directly suitable for . .proving.!. .Iadd.providing .Iaddend.thepotentials V_(high) and V_(low).

It will be apparent that in the above-described examples of suitableconstructions of the amplifier element 3, the amplifier element has biasgenerators 35 and 38 which provide gate electrode bias voltages oninternal biasing lines of the element. These bias voltages track theoutput terminal potential.

The potential levels of these internal biasing lines may be suitable fordirectly providing the required ON and OFF potentials for use incontrolling switching of the switch element 1, in which case thepotential generating circuitry 4 in the FIG. 3 circuit can of course beomitted entirely.

In other cases, the amplifier element may well have a pair of internalbiasing lines the potential difference between which is greater than orequal to the difference (V_(on) +V_(off)) between the required ON andOFF potentials. However, the respective potential levels of the internalbiasing lines of the pair may not always be suitable for providing theON and OFF potentials directly. Alternatively, one of the required ONand OFF potentials, for example the ON potential in the case ofenhancement type MOSFET switch element or the OFF potential in the caseof a depletion type MOSFET switch element, may on some occasions need tobe outside the supply lines of the circuitry.

These difficulties may be overcome by adopting a circuit constructionfor the amplifier element 3 and switch driving device 4, 5 as describedbelow with reference to FIG. 7.

In FIG. 7, the amplifier element 3 is made up mainly of enhancement typen-channel MOSFET transistors but is otherwise constructed in a similarmanner to the examples shown in FIGS. 4 and 5, and comprises a cascodedsource follower 31 and a current source 32 connected in series betweenthe positive supply line V_(dd) and the negative supply line V_(ss). Asbefore, the cascoded source follower 31 includes an input transistor 33and a cascoding transistor 341, plus a further transistor 342, connectedbetween the positive supply line V_(dd) and the drain electrode of thetransistor . .331.!. .Iadd.341.Iaddend., and a cascode bias generator 35comprising transistors 351 and 352 connected in series, together with anadditional transistor 353, between the positive supply line V_(dd) andthe source electrode of the transistor 33. In this case, the outputterminal OUT of the circuit is connected to the drain electrode of thetransistor 351 which, when the amplifier element is in use, ismaintained at substantially the same potential as the gate electrode ofthe transistor 33, i.e. at the voltage V_(c) of the upper plate of thestorage capacitor 2 connected to the gate electrode. In this respect,the transistors 342 and 353 are selected and connected so as toconstitute a PMOS current mirror which serves to decrease the amplifiergain error by ensuring that the current in transistor 351 is the same asthat in the input transistor 33, so that the output voltage closelyfollows the input voltage. It should be noted, however, that such use ofa PMOS current mirror is optional.

The amplifier element 3 of FIG. 7 has a first internal biasing line L1which is connected to the source electrode of the transistor 31. Whenthe circuit is in use, this internal biasing line will be maintained ata potential V₁ which is lower than the capacitor voltage V_(c) by anamount equal to the threshold voltage V_(T) of the transistor 31, i.e.V₁ =V_(c) -V_(T).

The amplifier element 3 has a further biasing line L' connected to thedrain of the transistor 351 of the cascode bias generator, which biasingline (as noted above) is maintained at substantially the capacitorvoltage V_(c) when the circuit is in use, but the potential differencebetween the internal biasing lines L1 and L' is only V_(T) which is lessthan the above-mentioned potential difference (V_(on) +V_(off)) betweenthe ON and OFF potentials required for controlling the switch element 1.However, the transistor 352 included between the transistors 351 and ..352.!. .Iadd.353 .Iaddend.in the cascode bias generator 35 operates togenerate, at a second biasing line L2 of the element, a potential V₂which is always greater than the output terminal potential V_(o) by anamount substantially equal to the threshold voltage V_(T) of thetransistor 352. The potential difference between the first and secondbiasing lines L1 and L2 is substantially equal to two transistorthreshold voltages 2V_(T), which potential difference is greater than orequal to the required difference (V_(on) +V_(off)) between the ON andOFF potentials of the switch element 1.

An example of switch driving device 4, 5 capable of employing thesepotentials V₁ and V₂ to generate the required ON and OFF potentials willnow be given. In this example the switch element 1 is of the n-channelenhancement type so that the OFF potential, V_(low), can be the outputterminal potential V_(o) itself, and the ON potential is V_(high)≈V_(low) +2V_(T). This ON potential can be greater than the positivesupply line V_(dd) in this example.

In FIG. 7, the potential generating element 4 includes a bootstrapcapacitor 44 and connecting element 45, comprising transistors 451 to453, connected for providing controllable connections between the platesof the bootstrap capacitor 44 and the internal biasing lines L1 and L2and the output terminal OUT.

The transistors 451 to 453 of the connecting means 45 each receive alogic signal SW which is at the high logic level when the switch element1 is to be OFF and at the low logic level when the switch element 1 isto be ON.

The logic signal SW is derived from the switching signal CK used tocontrol the switch element 1, so that it can be changed from the highlogic level to the low logic level in response to the switching signalCK.

The transistor 451 is a p-type transistor which is therefore turned ONwhen the logic signal SW is at the low logic level, whereas thetransistors 452 and 453 are n-type transistors which are thereforeturned ON only when the logic signal SW is at the high logic level.

The p-type transistor 451 is connected between the second biasing lineL2 and the negative plate of the bootstrap capacitor 44, the n-typetransistor 452 is connected between that plate and the first biasingline L1, and the n-type transistor 453 is connected between the positiveplate of the bootstrap capacitor 44 and the output terminal OUT.

The positive plate of the bootstrap capacitor 44 is permanentlyconnected to the gate electrode of the switch element 1.

Operation of switch driving device 4, 5 of FIG. 7 is as follows. Whenthe logic signal SW is at the high logic level to cause the switchelement to be in the OFF condition the n-type transistors 452 and 453are turned ON so that the positive plate of the bootstrap capacitor 44and the gate electrode of the switch element 1 are maintained at theoutput terminal V_(o) (=V_(low)) potential while the negative plate ofthe capacitor 44 is maintained at the potential V₁ (=V_(o) -V_(T)) ofthe first biasing line L1. Thus the bootstrap capacitor is charged to apotential substantially equal to V_(T).

If the logic signal SW is now changed, in response to the switchingsignal CK, from the high logic level to the low logic level to turn theswitch element ON, both of the n-type transistors 452 and 453 are turnedOFF, and the p-type transistor 451 is turned ON. Thus, the negativeplate of the bootstrap capacitor 44 undergoes a change in potential fromV₁ to V₂ at a time when its positive plate is isolated from the outputterminal potential V_(o). As a result, the positive plate potential isfree to float in accordance with the change (V₂ -V₁ ≈2V_(T)) in thenegative plate potential, and so the positive plate potential changes byV₂ -V₁. As a result the gate electrode potential of the switch element 1changes from the output terrors potential V_(o) (=V_(low)) to V_(o)+2V_(T) (=V_(high)), even if V_(o) +2V_(T) >V_(dd).

It should be noted that the capacitance of the bootstrap capacitor 44should be large compared to the gate capacitance of the switch element 1in order that the magnitude of the change in the potential at thepositive plate of the bootstrap capacitor 44 at the moment of switchingis not diminished unduly as compared with the corresponding change inthe potential at the negative plate thereof.

As described above, the use of a bootstrap capacitor and appropriateconnecting means, actuable in dependence upon the switching signal CKused to control switching, can enable the required ON and OFF potentialsto be derived from the potentials of internal biasing lines of thecircuit even when those lines do not have potentials that are suitablefor providing those ON and OFF potentials directly. The bootstrapcapacitor 44 can also permit these ON and OFF potentials to be outsidethe supply lines of the circuit. Moreover, the use of internal biasinglines which are necessarily already present in the circuit in thegeneration of the ON and OFF potentials can result in a worthwhilesaving in the amount of circuitry required.

Preferably, the voltage storage circuit of FIG. 3 is constructed as anintegrated circuit in order to make it possible to bootstrap theparasitic capacitances in the circuit, including the capacitance of theswitch element 1, the input capacitance of the amplifier element 3 andany interconnect capacitance.

To this end, the switch element 1, storage capacitance 2, and parts ofthe amplifier element 3 of the FIG. 3 circuit are advantageously formedin a well (denoted at 7 of FIG. 3) of opposite conductivity type to thatof the surrounding material of the substrate. For example, if theintegrated circuit is of the CMOS type having an n-substrate, the well 7in which the switch element 1, storage capacitor 2 and buffer element 3are formed will be of the p-conductivity type. The well is thenconnected so that its potential is substantially fixed in relation tothe upper plate potential V_(c) of the storage capacitor 2. For examplethe well may be connected electrically to the output terminal of thecircuit, as shown in FIG. 3.

FIGS. 8(A)-(B) illustrate one possible layout, within such an integratedcircuit, of the voltage storage circuit of FIG. 3 when the amplifierelement 3 is constituted substantially as shown in FIG. 4. As indicatedin FIGS. 8(A)-(B), the switch element 1, storage capacitor 2 and theinput transistor 33 and cascoding transistor 34 of the amplifier element3 are formed within a p-well 7p formed in a n-substrate 8n. The currentsource 32, current source bias generator . .33.!. .Iadd.38.Iaddend.(both not shown in FIGS. 8(A)-(B)), the cascode bias generator35 and switch driving means 4, 5 are formed outside the well 7p. Thecascode bias generator 35 and switch driving device 4, 5 mayalternatively also be within the well.

As shown in detail in FIGS. 8(A)-(B), the input voltage of the FIG. 3circuit is applied between an input terminal (IN) 11 and a commonterminal (COM) 12 thereof, the common terminal 11 being connected to thelower plate 21 of the storage capacitor 2. The upper plate 22 of thestorage capacitor 2 is connected to the gate electrode 33g of thetransistor 33 and also to the drain electrode 1d of the switchelement 1. The source electrode 1s of the switch element 1 is connectedto the input terminal (IN) 11.

The output terminal (OUT) 13 of the circuit is connected to the sourceelectrode 33s of the transistor 33, the transistor 33 being formed tohave a common channel 33c with the cascode transistor 34. The drainelectrode 34d of the cascoding transistor 34 is connected to thepositive supply rail V_(dd) and the gate electrode 34g thereof isconnected, by way of the cascode bias generator 35, to the outputterminal 13. The switch driving means 4, 5 are connected between theoutput terminal 13 of the circuit and the gate electrode 1g of theswitch element 1.

The p-well 7p is connected electrically to the output terminal 13 by ap⁺ contact region 9 provided within the p-well 7p at a location thereinadjacent to the n⁺ channel 33c, as shown in FIG. 8(B). A contact 10serves to connect the contact region 9 to the output terminal 13, asshown in FIG. 8(A). Also, as shown in FIG. 8(B) a shield 15 isoptionally provided over the devices within the well, which shield isalso connected electrically by contact 16 to the output terminal 13 ofthe circuit.

It will be appreciated that, since they are formed in a p-well in FIGS.8(A)-(B), the MOSFET switch element 1, and the transistors 33 and 34 ofthe amplifier element 3 must be of the n-channel type.

In the case of the amplifier element of FIG. 5, the cascoded sourcefollower 31 (comprising the FET input transistor 33, the cascodetransistors 341 and 342 and the transistors 351 to 353 of the cascodebias generator 35) is formed entirely within a P-well of the circuitcontaining the storage capacitor 2 and switch element 1. As before, thewell may, for example, be electrically connected to the output terminalOUT of the circuit. The current source 32 of the FIG. 5 amplifierelement will then be formed in a second p-well, which should beconnected electrically to a point in the circuit. The potential of whichis fixed in relation to the supply lines of the circuit, for example thenegative supply line itself.

It is not essential in the FIG. 3 circuit for the input switch element1, the storage capacitor 2 and the amplifier 3 to be formed together ina single well. In FIGS. 9(A)-(B), by way of example, the switch element1 and the storage capacitor 2 and the amplifier element 3 are formed indifferent respective p-wells 71p, 72p and 73p.

The swell 71p is connected electrically to the output terminal (OUI) 13of the cut by way of an auxiliary buffer element 17 and contacts 18 and19, so as to be at a potential substantially fixed in relation to theoutput terminal potential and hence in relation to the upper platepotential of the storage capacitor 2.

The p-well 72p is connected electrically to the bottom plate 21 of thestorage capacitor by way of contact 23 so as to be at a potentialsubstantially fixed in relation to the upper plate potential when theswitch element 1 is in the OFF condition.

The p-well 73p is connected electrically to the output terminal (OUT) 13of the circuit by contact 18 so that it is also at a potentialsubstantially fixed in relation to the upper plate potential of thestorage capacitor 2.

The parts 14, 24 of the interconnection portions between the circuitelements 1, 2 and 3 that are outside the wells 71p, 72p and 73p extendover interconnect shielding portions 151, 152 whose potentials aremaintained equal to the well potentials, thereby to eliminate parasiticcapacitances associated with the interconnection portions.

The well 72p for the storage capacitor 2 is optional.

A particularly advantageous application of a voltage storage circuit asdescribed hereinbefore with reference to FIGS. 3 to 7 will now bedescribed with reference to FIG. 10.

FIG. 10 shows voltage summation circuitry employing a voltage storagecircuit constituted as described hereinbefore with reference to FIG. 3.

The voltage summation circuitry includes, in addition, to the componentsof the FIG. 3 voltage storage circuit, an input isolation switch element46 connected in series with the input switch element 1 between thatelement and a first input node I₁, a selection switch element 47connected between, on the one band, respective second and third inputnodes I₂ and I₃ and, on the other hand, the common terminal COM of thevoltage storage circuit, and a feedback switch element 48 connectedbetween the output terminal OUT of the voltage storage circuit and theinput side of the input witch element 1.

An auxiliary capacitor 49 may optionally also be provided, connectedbetween the input side of the input switch element 1 and the commonterminal COM of the voltage storage circuit, in which case the feedbackswitch element 48 may be omitted.

In use of the voltage summation circuitry of FIG. 10, initially theswitch elements 1 and 46 are both controlled to be ON while the feedbackswitch element 48 is kept OFF. At this time, the selection switchelement 47 is configured to connect the second input node I₂ to thecommon terminal COM of the voltage storage circuit. The input switchelement 1 of the voltage circuit is then turned OFF, with the resultthat the potential difference V₁ -V₂ between the first and second inputnodes I₁ and I₂ at the moment of switching is stored in the storagecapacitor 2 of the voltage storage circuit

Thereafter, the input isolating switch element 46 is also turned OFF andthe feedback switch element 48 turned ON. As a result, the potential ofthe input side of the switch element ON is maintained substantiallyfixed in relation to the potential V_(c) of the upper plate of thestorage capacitor 2 after the input switch element 1 is turned OFF,irrespective of subsequent variations in the first input node potential.

If the auxiliary capacitor 49 is present between the input side of theinput switch element 1 and the terminal COM of the voltage storagecircuit, this auxiliary capacitor serves alternatively, or in addition,to the feedback switch element 48 to maintain the potential of the inputside of the input switch element 1 substantially fixed in relation tothe potential V_(c) of the upper plate of the storage capacitor 2 afterthe input switch element 1 is turned OFF.

Maintenance of the input side potential after switching OFF of the inputswitch element 1 is desirable to avoid the possibility of the inputswitch element 1 being turned ON again if the first input node potentialchanges sufficiently relative to the OFF potential applied to the gateelectrode of the input switch element 1.

At the same time as, or after, the input isolating switch element 46 isturned OFF, the configuration of the selection switch element 47 ischanged to connect the third input node I₃ to the common terminal COM inplace of the second input node I₂.

As a result, the output terminal potential becomes substantially equalto the third input node potential V₃ plus the stored difference V₁ -V₂between the first and second input node potentials, i.e.

    V.sub.o =V.sub.1 -V.sub.2 +V.sub.3 +V.sub.error

where V_(error) is an error voltage in the stored potential differenceV₁ -V₂ caused by charge injection by the input switch element 1 at themoment it is turned OFF. When, as discussed hereinbefore, the ONpotential applied to the input switch element I tracks the input nodepotential, this error voltage V_(error) is substantially constantirrespective of the potentials applied to the circuit, so that thiserror voltage can be compensated for in a desirably simple manner.

It will be appreciated that, by virtue of the effective elimination ofparasitic capacitance effects in the voltage storage circuit, thepotential of the lower plate of the storage capacitor can be changedfreely, after storage of a desired potential difference, withoutaffecting the stored potential difference in an unpredictable manner.This enables a voltage storage circuit constituted as describedhereinbefore with reference to FIG. 3 to provide particularly highaccuracy in voltage summation applications.

As a further advantageous application of the voltage storage circuit ofFIG. 3, FIG. 11 shows voltage doubling circuitry 50 including first andsecond voltage storage circuits VSC₁ and VSC₂ each constituted asdescribed hereinbefore with reference to FIG. 3.

The circuitry 50 has first and second input nodes I₁ and I₂ and firstand second output nodes O₁ and O₂. A first controllable switch element51 is connected between the first input node I₁ and input terminal IN₁of the first voltage storage circuit VSC₁. A second controllable switchelement 52 is connected between the second input node I₂ and commonterminal COM₁ of the first voltage storage circuit VSC₁.

A third controllable switch element 53 is connected between the firstinput node I₁ and common terminal COM₂ of the second voltage storagecircuit VSC₂. A fourth controllable switch element 54 is connectedbetween the second input node I₂ and input terminal IN₂ of the secondvoltage storage circuit VSC₂.

A fifth controllable switch element 55 is connected between therespective common terminals COM₁, COM₂ of the voltage storage circuitsVSC₁ and VSC₂.

The respective output terminals OUT₁ and OUT₂ of the first and secondvoltage storage circuits VSC₁ and VSC₂ are connected respectively to thefirst and second output nodes O₁ and O₂ of the circuitry 50.

The circuitry 50 further comprises control means 60 which apply a firstcontrol signal φ₁ to the switch elements 51 to 54 and a second controlsignal φ₂ to the switch element 55. The control means 60 also apply tothe voltage storage circuits VSC₁ and VSC₂ the above-mentioned switchingsignal CK used to control switching of the respective switch elements 1of the voltage storage circuits. The switch elements 51 to 54 arecontrolled to be in the ON condition when the control signal φ₁ isactive, and the switch element 55 is controlled to be in the ONcondition when the control signal φ₂ is active. The generation of theswitching signal CK applied to the switch driving means 4, 5 of each ofthe voltage storage circuits is synchronised by the control means 60with the switching of the control switch elements 51 to 55, such thatthe respective switch elements 1 of the voltage storage circuits VSC₁and VSC₂ are maintained in the ON condition when the switch elements 51to 54 are initially in the ON condition but are turned OFF before thoseelements 51 to 54 are switched to the OFF condition.

In operation of the FIG. 11 voltage doubling circuitry, the controlsignal φ₁ is initially activated so that the controllable switchelements 51 to 54 are initially switched to the ON condition, the switchelement 55 being OFF at this time. Thus, when φ₁ is active the switchelements 51 to 55 are in an input configuration which permits an inputvoltage V_(i) between the input nodes I₁ and I₂ to be applied betweenthe respective input and common terminals of each of the voltage storagecircuits VSC₁ and VSC₂.

While the switch elements 51 to 55 are in this input configuration, therespective switch elements 1 of the voltage storage circuits VSC₁ andVSC₂ are controlled by their associated switch driving device 4,5 to bein the ON condition. As a result, the respective storage capacitors 2thereof are each charged to the input voltage V_(i). In this respect, itis to be noted that the input voltage is applied with reverse polarityto the second voltage storage circuit VSC₂ as compared with the firstvoltage storage circuit VSC₁.

While the switch elements 51 to 54 are still turned ON, the controlmeans 60 apply the switching signal CK to the respective switch drivingmeans 4,5 of the voltage storage circuits in order to switch OFF therespective switch elements 1 of the voltage storage circuits. As aresult, the input voltage V_(is) at the moment of switching t_(switch)is stored in the respective storage capacitors 2 of the voltage storagecircuits.

Thereafter, the control means 60 deactivates the control signal φ₁, sothat the switch elements 51 to 54 are switched OFF, and then activatesthe control signal φ₂ so that the switch element 55 is switched ON. Inthis condition, the switch elements 51 to 56 are in an outputconfiguration. In this output configuration, the respective storagecapacitors 2 of the voltage storage circuits VSC₁ and VSC₂ are connectedin series between the respective inputs of the amplifier elements 3 ofthe voltage storage circuits VSC₁ and VSC₂. Since these amplifierelements 3 of the voltage storage circuits serve only to reproduce attheir respective outputs the potentials at their inputs, the outputvoltage V_(o) produced between the first and second output nodes O₁ andO₂ is substantially equal to double the stored input voltage Vis, i.e.V_(o) =2V_(is).

Accordingly, the circuitry 50 serves to provide an output voltage V_(o)which is substantially double the applied input voltage V_(i) at themoment of switching t_(switch).

The circuitry of FIG. 11 is capable of providing very high accuracy involtage doubling because the effects of parasitic capacitance in thecircuitry are minimised. This is because in a voltage storage circuitconstituted as described hereinbefore, the parasitic capacitances whichaffect the applied input signal (i.e. the capacitance of the inputswitch element 1, the capacitance at the input of the amplifier element3, and any interconnect capacitance in the voltage storage circuit) canall be bootstrapped In view of the fact that the voltage storagecircuits should preferably be formed in respective wells (to permitbootstrapping of the interconnect capacitance of the voltage storagecircuits), the entire voltage doubling circuitry 50 should preferably beformed as an integrated circuit.

It should be noted that this approach to voltage doubling isfundamentally different from that adopted in previously-consideredswitched-capacitor circuits used to perform voltage doubling. In thesepreviously-considered circuits, the circuit operation is designed to beinsensitive to parasitic capacitances by ensuring that all nodes in thecircuit are either driven by amplifiers (so that the parasiticcapacitances are charged by the amplifier outputs and have no effect),or are always returned to the same voltage on all clock phases ("virtualground" design so that no net charge flows into or out of the parasiticcapacitances). An example of the latter approach is provided inEP-B-0214831.

By designing the circuits to be insensitive to parasitic capacitances,the problems caused by parasitic capacitances per se are eliminated, butthe elision of parasitic problems leads to a different problem,associated with inevitable mismatch between the capacitors used to storeand double the input voltage which prevents desirably high accuracy frombeing achieved.

This problem arises because in previously-considered voltage doublingcircuits based on switched capacitors, the variable which is conservedduring a voltage doubling operation is charge (transferred from onecapacitor to another) rather than voltage as in the FIG. 11 circuitry.

Considering this problem in more detail, to double a voltage when chargeis conserved, a capacitor of value 2C (or two capacitors, each of valueC, in parallel) is charged to the input voltage, and then all the chargeis transferred to a single capacitor of value C (which may or may not beone of the originally-charged capacitors). Conservation of charge gives:

    2C.V.sub.in =C.V.sub.out

    V.sub.out =2V.sub.in

However, it is found that in practical circuits the output voltageV_(out) is not precisely double the input voltage V_(in), and this isdue to mismatch between the respective capacitances of the capacitorsused to perform the voltage doubling operation. In this respect, if therespective capacitances of the two capacitors that are charged to theinput voltage V_(in) are C₁ and C₂ respectively, and the capacitance C₃of a third capacitor which receives the combined charge stored in thosetwo capacitors is C₃, conservation of charges gives:

    (C.sub.1 +C.sub.2)·V.sub.in =C.sub.3 ·V.sub.out

    V.sub.out = (C.sub.1 +C.sub.2)/C.sub.3 !V.sub.in

Random mismatches between nominally identical capacitors are typicallybetween 0.1% (relatively easy to achieve on an integrated circuit) and0.01% (extreme precautions required, for example large capacitors splitinto units and interleaved). Such capacitance matching error results ina comparable error in the doubled voltage and, when the voltage doublingcircuit is employed in an analog-to-digital converter for example, thelinearity of the analog-to-digital converter can be limited to between10 and 13 bits by such error.

Error due to capacitance mismatch in such previously-consideredcharge-transfer based voltage doubling circuits can be eliminated byusing complicated switching arrangements. One previously consideredmethod is to charge a capacitor C₁ to the input voltage, transfer thecharge to a storage capacitor C₂, charge C₁ to the input voltage again,and then transfer all the charge back onto C₁. This results in an exactdoubling voltage of the input because the charge starts and finishes onthe same capacitor, but this method is more complex, slower (involvingmore clock phases), and more sensitive to amplifier switching noise.

Another previously-considered method is to "auto-calibrate", i.e.provide additional circuitry which measures the capacitor mismatch andadjusts for it. The provision of such circuitry, however, adds tocircuit complexity and reduces speed of operation.

Furthermore, the previously-considered voltage doubling circuits whichrely on charge transfer also rely effectively on the capacitors beinglinear, so that doubling the charge on a capacitor necessarily doublesthe voltage across it. Depending on the physical structure of thecapacitor, non-linearity of the capacitors used in thosepreviously-considered voltage doubling circuits can also limit thelinearity of the voltage doubling circuit as a whole.

In the FIG. 1 circuit, on the other hand, the requirement for highlylinear, accurately-matched capacitors is eliminated. Charging twocapacitors in parallel and then connecting them in series will alwaysexactly double the input voltage regardless of the matching andlinearity of the capacitors, provided that the effects of parasiticcapacitances can be cancelled out satisfactorily.

In the FIG. 11 circuitry, since the bootstrap switch driving device 4,5of each voltage storage circuit ensure that the charge injection of theswitch elements 1 is kept constant, then provided that the voltagestorage circuits are designed so that all parasitic capacitances thereinare driven by the amplifier element outputs, substantially the onlylimit on linearity of operation is gain error of the amplifier elements.This is because the parasitic capacitance cancellation is not fullyeffective if the gains of the amplifier elements of the voltage storagecircuits are not exactly unity. This gain error from exactly unityshould therefore be minimised.

In practice this gain error can be made as small as is required by thedesired precision of the particular voltage doubling application(although to obtain optimum accuracy a relatively complex amplifierelement construction will be required). By adopting a suitable amplifierelement construction this means that a linearity of at least 1ppm orbetter should be achievable, the actual performance limit beingdependent then upon random noise due to amplifier and thermal (kT/C)noise. In an analog-to-digital converter using such voltage doublingcircuitry, linearity could be maintained in excess of 20 bits.

Finally, by virtue of the back-to-back connection of two voltage storagecircuits VSC₁ and VSC₂ in the voltage doubling circuitry 50 of FIG. 11,the respective amounts of charge injected by the switch elements 1 ofthe circuits at the moment of switching effectively cancel out, makingthe circuitry self-compensating.

An example of the use of voltage doubling circuitry 50 such as thatshown in FIG. 11 will now be given with reference to FIG. 12.

FIG. 12 shows parts of an analog-to-digital converter (ADC) employingvoltage doubling circuitry as shown in FIG. 11. The FIG. 12 ADC is a"three-state logic" ADC.

A three-state logic ADC performs its analog-to-digital conversion bycarrying out a series of voltage conversion operations, starting with anapplied analogue input voltage, each involving a voltage doublingoperation. Digital data is produced in each such voltage conversionoperation, the digital data from the successive conversion operationsbeing combined to produce a digital output word representative of theapplied analog input voltage.

In each voltage conversion operation performed by a three-state logicADC, in a first phase of the operation an analog input voltage iscompared with a predetermined comparison potential V_(r) /4, where V_(r)is a predetermined reference potential, to produce one of three digitaldata values as indicated in Table 1 below.

                  TABLE 1                                                         ______________________________________                                        Result of Comparison                                                                           Digital Data                                                 ______________________________________                                         V.sub.r /4 ≦ V.sub.i                                                                   +1                                                           -V.sub.r /4 ≦ V.sub.i < V.sub.r /4                                                       0                                                            V.sub.i < -V.sub.r /4                                                                         -1                                                           ______________________________________                                    

Then, in a second phase of the operation, in dependence upon the digitaldata produced in the first phase the input voltage V_(i) is converted toproduce an analog conversion voltage V_(c) which is related to V_(i) bythe expressions indicated in Table 2 below.

                  TABLE 2                                                         ______________________________________                                        Digital Data   Analog Conversion Voltage V.sub.c                              ______________________________________                                        +1             2V.sub.i - V.sub.r                                              0             2V.sub.i                                                       -1             2V.sub.i + V.sub.r                                             ______________________________________                                    

In the next conversion operation this analog conversion voltage V_(c) isused as the analog input voltage, the conversion voltage V_(c)converging in successive such operations towards zero. Each successiveconversion operation produces one "bit" of three-state logic digitaldata (+1, 0, -1). An output word expressed in normal binary (two-state)logic can be derived from all the three-state bits in combination bysuitable digital logic circuitry, R three-state bits producing a binarylogic output word consisting of (R+1) bits.

A fuller description of the operation of a previously-consideredthree-state logic ADC is provided in "Fujitsu Facts: Three-states logiccontrols CMOS cyclic A/D converter is used in MB87020" by K. Gotoh andO. Kobayashi, and in EP-B-0214831, both of which documents areincorporated herein by reference.

The ADC of FIG. 12 comprises N voltage conversion stages ST₁, ST₂, . . .ST_(N) connected in series, each of which is capable of performing avoltage conversion operation as described above with reference to Table1 and 2. Only the first two such voltage conversion stages ST₁ and ST₂of the ADC are illustrated in FIG. 12.

Each of the stages ST_(i) is based upon voltage doubling circuitry 50'generally as described hereinbefore with reference to FIG. 11, the inputnodes I₁ and I₂ of the voltage doubling circuitry 50' providing inputnodes of the stage, and the output nodes O₁ and O₂ of the voltagedoubling circuitry 50' similarly providing output nodes of the stage.

The voltage doubling circuitry 50' of each stage ST_(i) differs from theFIG. 11 voltage doubling circuitry, however, in that in place of thesingle switch element 55 of the FIG. 11 circuitry, the voltage doublingcircuitry 55' has, connected in series between the respective commonterminals COM₁ and COM₂ of the two voltage storage circuits VSC₁ andVSC₂ of the circuitry, two controllable switch elements . .55.!..Iadd.56 .Iaddend.and . .56.!. .Iadd.57 .Iaddend.and voltage adjustmentmeans 58.

In each stage ST_(i), the switch elements 51 to . .56.!. .Iadd.54, 56and 57 .Iaddend.can be in either the above-mentioned input configuration(switch elements 51 to 54 in the ON condition whilst switch elements ..55.!. .Iadd.56 and . .56.!. .Iadd.57 .Iaddend.are in the OFF condition)or in the output configuration (switch elements . .55.!. .Iadd.56.Iaddend.and . .57.!. .Iadd.57 .Iaddend.in the ON condition whilstswitch elements 51 to 54 are in the OFF condition).

As in the case of the voltage doubling circuitry 50 of FIG. 11, theswitch elements 51 to .Iadd.54, .Iaddend.56 .Iadd.and 57 .Iaddend.ofeach stage ST_(i) are controlled by control signals φ₁ and φ₂. However,in the ADC of FIG. 12 control means 60' common to all the stages areprovided for generating the first and second control signals of eachstage and, when φ₁ is active the switch elements 51 to .Iadd.54,.Iaddend.56 .Iadd.57 .Iaddend.of the odd-numbered stages ST₁, ST₃, ST₅,. . . are maintained in the input configuration whilst the switchelements 51 to .Iadd.54, .Iaddend.56 .Iadd.57 .Iaddend.of theeven-numbered stages ST₂, ST₄, ST₆, . . . are maintained in the outputconfiguration, and vice versa when φ₂ is active.

Each voltage conversion stage ST_(i) also includes comparator means 70connected to the first and second input nodes I₁ and I₂ of the stage forreceiving the input voltage V_(i) applied to the stage and alsoconnected to receive the above-mentioned comparison potential V_(r) /4.The comparator means 70 provide at the output thereof three-state logicdigital data a (+1, 0, -1), serving as the digital output of the stage,in accordance with Table 2 above. The digital data of each stage isapplied to data processing means 80 for processing to produce a digitaloutput word. The digital data a is applied also to the voltageadjustment means 58 for controlling operation thereof.

The voltage adjustment means serve, when the switch elements . .55.!..Iadd.56 .Iaddend.and .Iadd.57 .Iaddend.are ON, to apply between therespective common terminals COM₁ and COM₂ of the voltage storagecircuits of the stage an offset voltage V_(os) selected, from one ofthree different possible voltages, by the digital data a produced by thecomparator means. In the case in which a=+1 (corresponding to the casein which V_(r) /4≦V_(i),) the selected offset voltage V_(os) =-V_(r).When a=0 (corresponding to the case in which -V_(r) /4≦V_(i) <V_(r) /4)the selected offset voltage V_(os=) 0. When a=-1 (corresponding to thecase in which V_(i) <-V_(r) /4) the selected offset voltage V_(os)=+V_(r).

In operation of the ADC shown in FIG. 12, an analog input voltage V_(i1)to be digitised is applied between the first and second input nodes I₁and I₂ of the first voltage conversion stage ST₁. Initially, the controlmeans 60' activates the control signal φ₁, so that the first voltageconversion stage ST₁ is maintained in the input configuration (switchelements 51 to 54 thereof ON). In this configuration the switch elements. .55 and.!. 56 .Iadd.and 57 .Iaddend.are both maintained in the OFFcondition, so that the voltage adjustment means 58 are isolated from therest of the circuitry.

While φ₁ is active the comparator means 70 of the first stage ST₁compare the applied input voltage V_(i) with the comparison potentialV_(r) /4 and produce three-state logic digital data a in dependence uponthe result of the comparison.

Before the end of the period during which φ₁ is active, the switchingsignal CK is applied by the control means 60' to each switch drivingdevice 4,5 of the first stage ST₁ to cause the respective switchelements 1 of the voltage storage circuits VSC₁ and VSC₂ of the stageST₁ to be switched OFF, with the result that the input voltage V_(i1)the first stage ST₁ is stored in each of the respective storagecapacitors 2 of those circuits.

The control means 60' then deactivates φ₁ and activates φ₂ to switch thefirst stage ST₁ to the output configuration. In this configuration, theswitch elements 51 to 54 of the stage are in the OFF condition, and theswitch elements . .55 and.!. 56 .Iadd.and 57 .Iaddend.of the stage arein the ON condition. The voltage adjustment means 58 are thereforeconnected in series between the respective storage capacitors 2 of thevoltage storage circuits VSC₁ and VSC₂, so that the selected offsetvoltage V_(os) (-V_(r), 0, +V_(r) depending on the digital data a) isapplied between the respective common terminals COM₁ and COM₂ of thevoltage storage circuits VSC₁ and VSC₂. Thus, an analog conversionvoltage V_(c) is produced between the first and second output nodes O₁,O₂ of the stage ST₁ which differs from double the stored input voltageV_(i1) by the selected offset voltage V_(os) applied between therespective common terminals COM₁, COM₂ of the voltage storage circuitsVSC₁ and VSC₂ by the voltage adjustment means 58 (i.e. V_(c1) =2v_(i1)+V_(os)).

Thus, in accordance with Table 2 above the conversion voltage V_(cl)produced by the voltage conversion stage ST₁ can be 2V_(i1) -V_(r),2V_(i1), or 2V_(i1) +V_(r), depending upon the result of the comparisonbetween V_(i1) and the comparison potential V_(r) /4.

As shown in FIG. 12, the voltage conversion stages of the ADC areconnected in series, so that the second voltage conversion stage ST₂receives as its input voltage V_(i2) the analog conversion voltageV_(cl) produced by the first voltage conversion stage ST₁. As notedabove, the switch elements 51 . .to 56.!. .Iadd.-54, .Iaddend.56.Iadd.,57 .Iaddend.of the second stage ST₂ are controlled φ₂ to be in the inputconfiguration when the switch elements 51 . .to 56.!. .Iadd.-.Iadd.54,.Iaddend.56.Iadd., 57 .Iaddend.of the first stage ST₁ are in the outputconfiguration, so that the second stage ST₂ can begin to perform itscomparison operation on the conversion voltage V_(cl) produced by thefirst stage ST₁ without delay. The switching signal CK for the switchdriving device 4,5 of the second stage ST₂ is accordingly generatedwhile φ₂ is active (rather than while φ₁ is active as was the case withthe switch driving device 4,5 the first conversion stage ST₁ ), so thatthe analogue conversion voltage V_(cl) of the first stage ST₁ is storedin the second stage ST₂. After the end of the period during which φ₂ isactive, φ₁ is activated again, causing the second stage ST₂ to beswitched to the output configuration. It therefore produces is analogueconversion voltage V_(c2) in dependence upon the analogue conversionvoltage V_(c1) of the preceding (first) stage.

The analog conversion voltage V_(c2) is applied to the input of the nextstage ST₃, and is converted in turn (during the next period during whichφ₁ is active) to an analogue conversion voltage V_(c3). Successivevoltage conversion operations are thus performed at each "swap" in theactivation of the control signals φ₁ and φ₂. The periods t₁ and t₂during which the control signals φ₁ and φ₂ are respectively activeconstitute first and second clock phases of the converter, the secondphase commencing after the end of the first clock phase in eachsuccessive clock period of the converter.

Since the first stage ST₁ is switched back to the input configurationwhen the second stage ST₂ is switched to the output configuration (toconvert the analog conversion voltage V_(c1) just provided by the firststage into the analog conversion voltage V_(c2)) a new analogue inputvoltage can be received by the converter each time φ₁ is reactivated. Inthis way, the ADC can produce a new conversion result (a digital outputword based on N three-state bits) in every clock period.

It is not essential that the comparator means 70 of a given stagedirectly compare the applied input voltage of the stage with thecomparison potential. The comparison could be between the ..comparator.!. .Iadd.comparison .Iaddend.potential, on the one hand,and, on the other hand, the input voltage as stored in the voltagestorage circuits, or an initial analogue conversion voltage provided bythe stage prior to the comparison (the analogue conversion voltagesubsequently being corrected).

In place of the N stages used in FIG. 12, it would alternatively bepossible to use just two voltage conversion stages operating iterativelywith each one alternatively sampling the output of the other. Thisarrangement would take one clock period (i.e. 2 clock phases) to produceevery two bits of three-state logic digital data. Thus, to perform an Nbit conversion, the arrangement would take N/2 clock periods, which ismuch slower than a converter employing N stages. The amount of circuitryrequired would however be decreased.

In a different aspect of the present invention, it is also possible toconstruct a three-state logic ADC employing just one voltage conversionstage operating iteratively, although in this case the voltageconversion stage must employ voltage storage circuits constructeddifferently from the voltage storage circuits in the conversion stagesST_(i) in the FIG. 12 ADC, as described below with reference to FIG. 13.

In FIG. 13 a voltage conversion stage 90 for use in a three-state logicADC includes first and second modified voltage storage circuits VSC₁ 'and VSC₂ ' connected respectively to first and second input nodes I₁ andI₂ of the voltage conversion stage 90.

Each modified voltage storage circuit includes an input switch element1, a unity-gain amplifier element 3 and bootstrapped switch drivingdevice 4, 5 as described hereinbefore with reference to FIGS. 3 to 9(B).However, in place of the single capacitor 2 in the voltage storagecircuit of FIG. 3, each modified voltage storage circuit includes twocapacitors, labelled C₁ and C₃ in the case of the first modified voltagestorage circuit VSC₁ ', and C₂ and C₄ in the case of the second modifiedvoltage storage circuit VSC₂ '. The capacitors C₁ to C₄ are normally ofthe same capacitance, but this is not essential for correct operation ofthe voltage conversion stage 90.

Each modified voltage storage circuit also includes a number of switchelements 91 to 106, there being four switch elements associated witheach capacitor C₁ to C₄. Thus, the switch elements 91, 92, 95 and 96 areassociated with the capacitor C₁, the switch elements 101, 102, 105 and106 are associated with the capacitor C₂, the switch elements 93, 94, 97and 98 are associated with the capacitor C₃, and the switch elements 99,100, 103 and 104 are associated with the capacitor C₄.

The switch elements 91 to 106 are turned on and off in accordance withcontrol signals φ₁ and φ₂ produced by the bootstrapped switch drivingmeans, as explained in more detail hereinafter.

Associated with each modified voltage storage circuit VSC₁ ' or VSC₂ 'is an input isolation switch element 46 connected in series with theinput switch element 1 between that element and the relevant input nodeI₁ or I₂ of the voltage conversion stage 90, and a feedback switchelement 48 connected between an output node of the modified voltagestorage circuit (at the output terminal of the amplifier element 3) andthe input side of the input switch element 1. The input isolation switchelement 46 and feedback switch element 48 correspond to the switchelements of the same name and reference numeral in the voltage summationcircuitry of FIG. 10, and serve the same purpose. The feedback switchelements 48 can alternatively be replaced by resistors.

Voltage adjustment means 58, generally similar to the voltage adjustmentmeans 58 in FIG. 12, are connected between the first and second modifiedvoltage storage circuits VSC₁ ' and VSC₂ '. Furthermore, comparatormeans 70, similar to the comparator means of each voltage conversionstage ST_(i) in FIG. 12, are connected between the respective outputnodes of the modified voltage storage circuits.

The voltage adjustment means 58 includes a further plurality of switchelements 581 to 588. The six switch elements 582 to 584 and 586 to 588are activated in pairs in dependence upon the logic level of thethree-state data "bit" a_(i) produced by the comparator means. In thisway, when a_(i) =-1 the switch elements 582 and 586 are activated and asa result an offset voltage V_(os) generated between the output terminalsof the voltage adjustment means 58 is equal to +V_(r), where V_(r) is apredetermined reference voltage; when a_(i) =0 the switch elements 583and 587 are activated and the offset voltage V_(os) is zero; and whena_(i) =+1 the switch elements 584 and 588 are activated and the offsetvoltage V_(os) is equal to -V_(r).

The activation of the other two switch elements 581 and 585 in thevoltage adjustment means 58, which are connected respectively to thesecond and first input nodes I₂ and I₁ of the stage 90, will beexplained below.

Control means 61, generally similar to the control means 60' in FIG. 12,are operative to generate not only master control signal φ_(1M) andφ_(2M), but also respective further master control signals SAM_(M) andCON_(M). The master control signals φ_(1M), φ_(2M) SAM_(M) are appliedto the bootstrapped switch driving means 4,5 of each modified voltagestorage circuit. The bootstrapped switch driving means of each modifiedvoltage storage circuit generate bootstrapped control signals φ₁, φ₂ andSAMPLE, in accordance with the corresponding master control signalsφ_(1M), φ_(2M) and SAM_(M), for application to the switch elements ofthe modified voltage storage control signals tracking the outputterminal potential of the amplifier element 3 in the modified voltagestorage circuit. A further control signal CONVERT, used to activate thefeedback switch element 48 associated with each modified voltage storagecircuit, may be a bootstrapped control signal derived from the mastersignal CON_(M), but can alternatively be provided directly by the mastersignal CON_(M) since it is not essential for the signal applied to thefeedback switch elements 48 to be bootstrapped.

At the start of a conversion operation by the voltage conversion stage90 of FIG. 13, an analogue input voltage to be converted into itsdigital equivalent is applied between the first and second input nodesI₁ and I₂ of the voltage conversion stage 90. To facilitate sampling ofthe applied analogue voltage, the control means 61 generates the mastercontrol signal SAM_(M) which activates the associated bootstrappedcontrol signals SAMPLE in each modified voltage storage circuit toconnect the input nodes I₁ and I₂ via the switch elements 1 and 46 tothe respective inputs of the amplifier elements 3 in the modifiedvoltage storage circuits. At this time, the CONVERT control signal isdeactivated, so that the feedback switch elements 48 are in the offcondition

The switch elements 581 and 585 in the voltage adjustment means 58 arealso activated by the control signal SAMPLE, so that the output terminalpotentials of the voltage adjustment means are equal respectively to thepotentials of the second and first input nodes I₂ and I₁. The otherswitch elements 582 to 584 and 586 are maintained in the off conditionat this time.

Assuming that during sampling of the input voltage the control signal φ₁is active, the switch elements 91, 95, 101 and 105 will be in the oncondition, so that the capacitor C₁ in the first modified voltagestorage circuit VSC₁ ' has its top plate connected to the first inputnode I₁ and its bottom plate connected to the second input node I₂.Similarly the capacitor C₂ in the second modified voltage storagecircuit VSC₂ ' has its top plate connected to the second input node I₂and its bottom plate connected to the first input node I₁. Eachcapacitor C₁ and C₂ therefore stores the applied analogue input voltage,so as to achieve sampling of that input voltage.

Whilst the control signal φ₁ is active, the switch elements 94, 98, 100and 104 are in the on condition, so that the capacitors C₃ and C₄ areconnected in parallel with one another between the respective outputterminals of the amplifier elements 3. Because the amplifier elementshave unity gain, the sampled analogue input voltage is also stored ineach of the capacitors C₃ and C₄ during φ₁.

The SAMPLE control signal is then deactivated, so as to terminate thesampling of the input voltage, the control signal φ₁ remaining active.

After the SAMPLE control signal is deactivated, the CONVERT controlsignal is activated for the remainder of a conversion operation. Becausethe input and output terminal potentials of the unity-gain amplifierelement 3 are always equal, the input-side and output-side terminals ofthe input switch element 1 are maintained at the same potential, so thatelement 1 is maintained safely in the off condition, irrespective ofsubsequent changes in the potential of the associated input node I₁ orI₂.

The sampled input voltage which is held by the capacitors C₃ and C₄, iscompared by the comparator means 70 with a predetermined comparisonpotential V_(r) /4 in the same way as in the FIG. 12 ADC. A first "bit"a₁ of three logic digital data (+1, 0, -1) is produced by the comparatormeans 70 in dependence upon the result of the comparison (see Table 1above).

After the first data bit a₁ is obtained, a pair of the switch elements582 to 584 and 586 to 588 in the voltage adjustment means 58 isactivated according to the first data bit a₁. The voltage adjustmentmeans 58 thus produces one of its predetermined offset voltages V_(os)(-V_(r), 0, +V_(r) depending on the digital data bit a₁) between itsoutput terminal. With the control signal φ₁ still active, the switchelements 91, 95, 101, and 105 are all still in the on condition, so thata first series connection now exists between the respective inputterminals of the switch elements 3. This first series connectionconsists of the capacitor C₁, the voltage adjustment means 58 and thecapacitor C₂. Thus, the voltage between the respective input terminalsof the amplifier element 3 is a first conversion voltage V_(c1) equal totwice the sampled analogue input voltage stored in the capacitors C₁ andC₂ plus the offset voltage V_(os) selected by the first data bit a₁. Inthis way, a voltage conversion operation, in accordance with Table 2above, is performed.

The input terminal potentials of the amplifier elements 3 are bufferedby the amplifier elements 3, so that the first conversion voltage V_(c1)is reproduced between the respective output terminals of the amplifierelements 3.

The switch elements 94, 98, 100 and 104 are all still in the oncondition, so that the capacitors C₃ and C₄ are connected in parallelwith one another between the respective output terminals of theamplifier elements 3, and each store the first conversion voltageV_(c1).

The first conversion voltage V_(c1) is compared by the comparator means70 with the comparison potential V_(r) /4, and a second data bit a₂ isproduced in dependence upon the result of the comparison.

The control means then deactivates the control signal φ₁ and activatesthe control signal φ₂. At the same time, the second data bit a₂ isapplied to the voltage adjustment means to select a new offset voltageV_(os) in accordance with that data bit a₂. With φ₂ active the switchelements 93, 97, 99 and 103 are in the on condition. As a result, thecapacitors C₃ and C₄ are connected in series with the voltage adjustmentmeans 58 to form a second series connection (C₃ -V_(os) -C₄), in placeof the first series connection (C₁ -V_(os) -C₂) mentioned above, betweenthe respective input terminals of the amplifier elements 3. Theresulting new conversion voltage V_(c2), produced between the respectiveoutput terminals of the amplifier elements 3, is therefore equal totwice the first conversion voltage V_(c1) plus the new selected offsetvoltage V_(os). With φ₂ active the switch elements 92, 96, 102 and 106are in the on condition, so that this new conversion voltage V_(c2) isstored in the capacitors C₁ and C₂ which are connected in parallelbetween the respective output terminals of the amplifier elements 3.

The new conversion voltage V_(c2) is compared with the comparisonpotential V_(r) /4 in the comparator means 70 to produce the nest databit a₃. The control signal φ₂ is then deactivated the control signal φ₁is activated, and the data bit a₃ is applied to the voltage adjustmentmeans to select a new offset voltage V_(os). With φ₁ active the firstseries connection (C₁ -V_(os) -C₂) replace the second series connection(C₃ -V_(os) -C₄) between the amplifier element input terminals and thecapacitors C₃ and C₄ store the resulting new conversion voltage V_(c3).

Thereafter, the control signals φ₁ and φ₂ are activated alternatively, anew data bit a_(i) and new conversion voltage being produced during eachsuccessive control signal phase.

As described before with reference to FIG. 12, the data bits a_(i) areapplied to data processing means 80 (not shown) of the ADC forprocessing to produce a digital output word representative of theoriginally-applied analogue voltage. It will be understood that the FIG.13 voltage conversion stage requires N clock phases to produce a digitaloutput word based on N three-state bits.

It will be appreciated that the switch elements 1, 48, 91, 92, 93 and 94in the first modified voltage storage circuit VSC₁ ', and thecorresponding switch elements 1, 48, 103, 104, 105 and 106 in the secondmodified voltage storage circuit VSC₂ ', each have no voltage acrosstheir two terminals when either φ₁ or φ₂ is active, since, for eachamplifier element 3, the input terminal potential is equal to the outputterminal potential.

The switch elements 91 to 94 and 103 to 106 connected to the capacitortop plates can switch without non-overlap (i.e. without delay afterswitch-off of, say, element 91 before element 92 can be switched on)since all of the four nodes to which these elements are connected(amplifier element input terminal, amplifier element output terminal,and the respective top plates of the two capacitors) have the samevoltage before and after switching (i.e. before and after each controlsignal phase change from φ₁ to φ₂ or vice versa). This ability to switchthe top plate switches 91 to 94 and 103 to 106 without nonoverlapsimplifies the generation of the control signals.

It should be noted that the switches 95 to 102 connected to thecapacitor bottom plates should be switched a predetermined short timeafter switching of the switch elements 91 to 94 and 103 to 106 connectedto the capacitor top plates, in order to avoid charge injection effects.The predetermined short time should be minimised in view of the factthat during this time the input terminal of each amplifier element 3 iseffectively coupled to the output terminal of the other amplifierelement, so that positive feedback can occur. The effects of thispositive feedback are not serious in view of the fact that the amplifierelements have unity gain, but none the less it is preferable to avoidleaving the voltage conversion stage 90 in this condition for longerthan is absolutely necessary. Thus, as soon as the top plate switchelements 91 to 94 and 103 to 106 have settled, the bottom plate switchelements 95 to 102 are switched.

The switch elements 1 and 91 to 94 in the first modified voltage storagecircuit VSC₁ ' should preferably be formed in one or more wells of theopposite conductivity type to that of the surrounding material of thesubstrate, the potential of the or each well being fixed in relation tothe output terminal potential of the amplifier element 3 in the firstmodified voltage storage circuit. The same applies to the switchelements 1 and 103 to 106 in the second modified voltage storage circuitVSC₂ '. This arrangement of the switch elements enables parasiticcapacitances in the modified voltage storage circuit to be bootstrappedout, in the same basic manner as described hereinbefore with referenceto the voltage storage circuit of FIGS. 3 to 9.

In the FIG. 13 voltage conversion stage, the first voltage conversionoperation is performed during the initial clock phase in which theanalogue input voltage is sampled, immediately after sampling iscomplete. This speeds up operation of the converter, but does requirethe provision of extra switch elements (the elements 581 and 585 shownincorporated in the voltage adjustment means 58) to charge the capacitorbottom plates of the capacitors C₁ and C₂ to the input node potentialsduring sampling. It would be possible to omit these switch elements 581and 585 and simply perform a comparison operation in the initial clockphase (to obtain a₁), the first voltage conversion operation beingperformed in the next clock phase.

A voltage conversion stage as described above with reference to FIG. 12or 13 is applicable, with suitable modifications, to otheranalogue-to-digital converters that require voltage doubling andoffsetting operations.

In order to minimise power consumption of an ADC employing a series ofvoltage conversion stages as described above with reference to FIG. 12,it is advantageous to "scale" successive stages. This will now bediscussed in more detail with reference to FIG. 14.

In FIG. 14 the first three stages of an ADC as shown in FIG. 12 arerepresented schematically. The storage capacitors 2 in the first stageeach have a capacitance C, the transistors in the amplifier element 3are each of channel width W, and the current flowing through each ofthose transistors in the amplifier element 3 is I.

In the second stage, the storage capacitors 2 are each of capacitancekC, where 1/k is a predetermined scaling factor (k<1) the transistors inthe amplifier elements 3 are each of width kW, and the current flowingthrough each transistor is kI. Similarly, in the third stage thecapacitance is k² C, the transistor channel width k² W, and thetransistor current k² I.

Thus each successive stage is scaled, at least insofar as these threeparameters are concerned, by the scaling factor 1/k. As a result, thetotal current consumed in the device, expressed in relation to thecurrent consumed by the first stage, is

    1+k+k.sup.2 +k.sup.3+  . . .

Each stage has a noise power at its own input of 1/k but, relative tothe input terminal of the ADC, this is reduced by the product of thegains of the preceding stages. For example, the second stage noisepower=1/k, the voltage gain of the preceding stages (in this case thevoltage gain of the first stage)=2, and hence the noise power, relativeto the input noise power, is 1/4k.

Thus, total noise power at the input for all the stages is ##EQU1##

When k=1/2, for example, total noise=1+1/2+1/4+1/8 . . . =2

Similarly substituting k=1/2 in the total current equation above, totalcurrent=1+1/2+174+1/8 . . . =2

For a constant total power all sizes must then be divided by the resultof the power summation, i.e. input noise is multiplied by the samefactor. ##EQU2## This is a minimum when m=1, i.e. k=1/2.

From the above analysis, it will be apparent that the optimum scalingfactor for minimum, total power consumption of the ADC should be 2. Thisprovides a minimum noise level for a given power consumption or aminimum power consumption level for a given noise level Thus, each stageshould be substantially half the size of the preceding one In this casethe total power consumption equals two times the power consumption ofthe first stage, and the total noise power equals two times the firststage noise power.

FIG. 15 shows the variation of total current and noise with the scalingfactor 1/k in the case of a 16 stage ADC. As FIG. 15 shows, the noiseminimum for a given power consumption and the power consumption minimumfor a given noise level each occur when the scaling factor 1/k=2.

Although the analysis presented above suggests that scaling of theconversion stages should be applied to all stages of the ADC, inpractice scaling of stages cannot continue to the final stage, since fora 16 stage series (17 bit ADC) this would mean that the last stage was1/2¹⁶ =1/65536 times the size of the first stage.

At a particular stage in the series, when the stage size has becomesuitably small all the succeeding stages are made the same size, thisincreases the noise slightly but means that a huge range of sizes is notrequired.

For example, if scaling stops after six stages, the smallest stage size(used in the sixth and all successive stages) is 1/32 relative to thesize of the first stage. In this case total power=

    1+1/2+1/4+1/8+1/16+1/32+1/32+1/32 . . .

Once a minimum stage size is selected, a stage of such size can bedesigned as a "unit" stage that can be paralleled up (or "stretched" inlayout) to form the bigger stages. For example, if the unit stage is ofsize 1/32 relate to the first stage:

first stage=32 parallel units

second stage=16 parallel units

third stage=8 parallel units

One possible layout on a chip of an ADC employing a unit stage of size1/32 is shown in FIG. 16.

For a given minimum size of stage, the optimum scaling factor 1/k isstill very close to 2, as will be clear from Table 3, which presents theoptimum scaling factors for different smallest stage sizes in the caseof a 15 stage ADC (16 bits).

Compared to the optimum noise power figure of 4.0 when scaling is notstopped, a smallest stage size of 1/32 results in a total power increaseor noise increase of around 10% or 0.46 dB, whereas a minimum stage sizeof 1/16 increases the power or noise by around 25% or 0.99 dB. These twominimum stage sizes would appear to be good compromises.

                  TABLE 3                                                         ______________________________________                                        Smallest Stage                                                                              Minimum     Optimum                                             Size          overall noise                                                                             scaling factor                                      (first stage = 1)                                                                           (noise at k = 1/2)                                                                        (l/k)                                               ______________________________________                                        small         4.0  (4.0)  2.0                                                 1/256         4.03 (4.04) 1.99                                                1/128         4.08 (4.08) 1.99                                                1/64          4.19 (4.19) 1.97                                                1/32          4.44 (4.45) 1.92                                                1/16          4.97 (5.02) 1.83                                                1/8           6.05 (6.23) 1.68                                                ______________________________________                                    

Scaling such as that described above can usually be applied, in anotheraspect of the present invention, to any suitable kind ofanalogue-to-digital converter employing a series of voltage conversionstages. For example, it would be possible to apply scaling to thevoltage conversion circuits described in EP-B-0214831 in a case in whicha plurality of stages as described in that document were connectedtogether as a series.

The current consumed by the ADC of FIG. 12 is directly proportional tothe capacitance of the storage capacitors 2 and inversely proportionalto conversion rate. This means that for higher resolution and higherconversion rates the power is of course increased. However, it isestimated that a 16 bit 10 Ms/s converter would consume less than 0.5 W.This suggests that by reducing the conversion rate to 1 Ms/s, the powercould be reduced to 50 mW, or 5 mW at 100 ks/s.

For lower resolutions (for example 12 bits), the power and area decreaserapidly since the capacitance can be much smaller; a 12 bit 50 Ms/sconverter is estimated to consume 200 mW including the power consumptionof the digital logic circuitry required to process the digital dataprovided by the different conversion stages.

This represents a much improved power/speed trade-off relationship ascompared with previously-considered converters. One major reason forthis is that each stage m the series can be half the size and power ofthe previous stage, giving a total power for the converter which isapproximately double that of the first stage. This also gives a bigreduction in chip size: it is estimated that a 16 bit 10 Ms/s converterwould occupy less than 10mm² in a suitable process.

In addition to the voltage doubling circuitry and comparator means, thedigital logic circuitry for a N-bit output word ADC comprise (N-1)²D-type flip-flops and (N-1) full adders, all clocked at the conversionrate. For a 16-bit resolution this gives a basic cell count of about2000, and a power consumption at 5 V and 10 MHz of about 25% of theestimated analogue power consumption at 16 bit resolution (for 15 bitresolution the analogue power consumption would be reduced by a factorof 4).

As noted above, the gain of each of the amplifier elements 3 of thevoltage conversion stages of the ADC should be exactly unity. If theyare not, apart from giving rise to a gain error in the transferfunction, an additional gain error results because the parasiticcapacitances will not be completely bootstrapped out Non-linearityresulting from these errors can be corrected for by adjusting thereference voltage V_(r) used by each stage slightly along the series ofstages, for example, to correct for a 0.1% gain error, V_(r) may bereduced by 0.1% for each successive stage.

Alternatively, or in addition, the digital data processing means 80receiving the digital data from each stage may carry out any requiredcorrection for voltage conversion errors in the analogue circuitry byadjusting the digital data of the successive stages fractionally.

In order to produce an ADC capable of high speed operation, it isessential that the operation of the switch elements and of the amplifierelements in the stages is sufficiently fast. The unity-gain amplifierelements 3 can be designed to be much faster than conventionaloperational amplifiers, and SPICE simulations have indicated that asettling time of 50 ns (corresponding to a conversion rate of 10 Ms/s)is practical to 16 bit accuracy in a suitable process. Using depletionmode NMOS buffers and sacrificing some resolution, settling times of 10ns can be obtained to 12 bit accuracy. This suggests that ADCs based onthe FIG. 12 design could be employed in applications such as HDTV.

Circuit noise is not a serious problem in the FIG. 12 ADC, because thenoise due to the amplifier elements is effectively reduced by virtue ofthe doubling of the analogue input voltage before it reaches theamplifier elements. It is conceivable that the amplifier elements can bedesigned so that they contribute less noise than kT/C noise This kT/Cnoise is due to thermal noise which limits the accuracy of a givenstored voltage sample in any switched capacitor circuit, and preventsvery small capacitors from being used. It is estimated that for a 16 bitsignal to noise ratio, storage capacitors of at least 10 pF are requiredin the fist stage, reducing by half in each subsequent stage.

For maximum performance, the FIG. 12 ADC is preferably produced by ap-well (n-substrate) CMOS process, desirably using depletion-modedevices.

It is difficult to obtain sufficiently large voltage swings even with asingle 5 V power supply (lower voltage swings mean that lower noiselevels are required in the circuitry making up the different stages),and this problem is exacerbated with still lower supply voltages such as3.3 V.

However, none of the devices in the ADC are exposed to full supplyvoltage because they are connected in series; only the source/draindiodes are subjected to a higher voltage and even this is not as largeas the supply voltage. The largest voltage (5 V) is produced across thewell-substrate junction. In view of this, it may be advantageous to usesplit ±3 V (or ±3.3 V) supplies, with the digital circuits (of minimumGeometry) running from 0 V and +3 V, and the analogue circuits using ±3V. This split-supply approach also has the major advantage that theinput signals can swing either side of 0 V and so can be DC coupled. Thedigital power consumption is also reduced in accordance with thereduction in the effective digital logic supply voltage and this couldgive a significant reduction in total power consumption.

Smaller geometry processes can permit an increase in maximum clock ratethough not if this is limited by analogue power consumption. The mainadvantage of split power supplies is therefore increased digital speedand reduced power consumption which would increase the maximum speed ofoperation of the ADC.

What we claim is:
 1. A voltage storage circuit comprising:a storagecapacitor, one plate of which is connected to an input terminal of thecircuit by way of an input switch element and the other plate of whichis connected to a common terminal of the circuit, to store an inputsignal being applied between said input and common terminals when thecircuit is in use; . .and.!. an amplifier element, having an inputconnected to said one plate and an output connected to an outputterminal of the circuit, for providing an output signal, between saidoutput and common terminals, dependent upon the voltage stored in saidstorage capacitor, which amplifier element includes an electronic inputdevice having a controllable current path provided between respectivefirst and second current-path electrodes of the electronic input deviceand also having a control electrode to which a potential is applied tocontrol the magnitude of current in said controllable current path, saidcontrol electrode being connected to said one plate, and said first andsecond current-path electrodes being connected with a potential trackingdevice such that both the first current-path electrode potential and thesecond current-path electrode potential track the control electrodepotential, whilst current flows in said controllable current path, sothat the respective potentials of the first and second current-pathelectrodes are kept substantially fixed in relation to the potential ofsaid one plate.Iadd., said voltage storage circuit being formed on asingle substrate, and said input switch element and said input device ofthe amplifier element being located within one or more wells of theconductivity type opposite to that of the surrounding material of saidsubstrate; and means for causing each well potential to track thepotential of said one plate.Iaddend..
 2. A voltage storage circuit asclaimed in claim 1, wherein the potential tracking device includes acurrent source, connected to the said first current-path electrode forcausing the first current-path electrode potential to track the controlelectrode potential, and active follower means connected operativelybetween the said first and second current-path electrodes for causingthe second current-path electrode potential to track the firstcurrent-path electrode potential.
 3. A voltage storage circuit asclaimed in claim 2, wherein the said electronic input device is an FETinput transistor and the said control electrode is the gate electrode ofthe FET input transistor, the first current-path electrode is the sourceelectrode of the FET input transistor, the said second current-pathelectrode is the drain electrode of the FET input transistor, and thesaid controllable current path is provided by the drain-source channelof the FET input transistor.
 4. A voltage storage circuit as claimed inclaim 3, wherein the said active follower means comprise a cascoding FETtransistor connected with its drain-source channel in series with thedrain-source channel of the said FET input transistor so that the sourceelectrode potential of the cascoding transistor tracks the gateelectrode potential thereof and also comprise a bias generator connectedoperatively between the source electrode of the FET input transistor andthe gate electrode of the cascoding transistor for maintainingtherebetween a substantially constant potential difference.
 5. A voltagestorage circuit as claimed in claim 2, wherein the said amplifierelement is made up of first and second substantially identical circuitportions, the first portion including the said input device and the saidactive follower means and the second portion including the said currentsource.
 6. A voltage storage circuit as claimed in claim 1, wherein thesaid input switch element is an electronic input switch element,operative in dependence upon the potential at a switching electrodethereof, the circuit further including switch driving means connected tocause the switching electrode potential to track the input terminalpotential when the element is in its ON condition, thereby maintainingthe switching electrode potential substantially fixed in relation to theinput terminal potential, and operable to cause the switching electrodepotential to change, relative to the input terminal potential such thatthe element is changed from its ON condition to its OFF condition.
 7. Avoltage storage circuit as claimed in claim 6, wherein the saidswitching electrode potential is derived from the said output signal. 8.A voltage storage circuit as claimed in claim 7, wherein the said switchdriving means are connected operatively with the said output terminaland are operable, in dependence upon a switching signal receivedthereby, to apply to the said switching electrode either an ONpotential, for maintaining the said input switch element in its ONcondition, or an OFF potential, for maintaining the said input switchelement in its OFF condition, the said ON and OFF potentials being eachsubstantially fixed in relation to the said output terminal potentialbut differing from one another by a predetermined amount.
 9. A voltagestorage circuit as claimed in claim 8, having respective first andsecond biassing lines connected operatively to the said output terminalso as to be at potentials that are respectively fixed in relation to theoutput terminal potential, the second biassing line potential beingequal to one of the said ON and OFF potentials and the potentialdifference between the said first and second biassing lines beinggreater than or equal to the said predetermined amount, wherein the saidswitch driving means include a bootstrap capacitor one plate of which isconnected to the said switching electrode for providing the saidswitching electrode potential and also include connecting meansconnected with both plates of the bootstrap capacitor and with the saidbiassing lines and switchable, when the switching electrode potential isto be changed from the said one of its ON and OFF potentials to theother of those potentials, from a charging configuration, serving toconnect the said one plate of the bootstrap capacitor to the said secondbiassing line whilst connecting the other plate thereof to the saidfirst biassing line, to a floating configuration serving to isolate thesaid one plate from the second biasing line whilst connecting the saidother plate to the said second biassing line, thereby to cause thepotential at the said one plate to be changed from the second biassingline potential to a potential differing therefrom by the aidpredetermined amount.
 10. A voltage storage circuit as claimed in claim8, having respective first, second and third biasing lines connectedoperatively to the said output terminal so as to be at potentials thatare respectively fixed in ration to the output tern potential, the thirdbiassing line potential being equal to one of the said ON and OFFpotentials and the potential difference between the said first andsecond biassing lines being greater than or equal to the saidpredetermined amount, wherein the said switch driving means include abootstrap capacitor one plate of which is connected to the saidswitching electrode for providing the said switching electrode potentialand also include connecting means connected with both plates of thebootstrap capacitor and with the said biassing lines and switchable,when the switching electrode potential is to be changed from the saidone of its ON and OFF potentials to the other of those potentials, froma changing configuration, serving to connect the said one plate of thebootstrap capacitor to the said third biassing line whilst connectingthe other plate thereof to the said first biassing line, to a floatingconfiguration serving to isolate the said one plate from the thirdbiassing line whilst connecting the said other plate to the said secondbiassing line, thereby to cause the potential at the said one plate tobe changed from the third biassing line potential to a potentialdiffering therefrom by the said predetermined amount.
 11. A voltagestorage circuit as claimed in claim 8, wherein the said electronic inputswitch element is a MOSFET transistor and one of the said ON and OFFpotentials is substantially the same as the said output terminalpotential. . .12. A voltage storage circuit as claimed in claim 1,formed on a single substrate, wherein the said input switch element andthe said input device of the amplifier element are located within one ormore wells of the conductivity type opposite to that of the surroundingmaterial of said substrate, there being means for causing the or eachwell potential to track the potential of the said one plate..!.13. Avoltage storage circuit as claimed in claim . .12.!. .Iadd.1.Iaddend.,wherein the said storage capacitor is also located within such a well.14. A voltage storage circuit as claimed in claim . .12.!..Iadd.1.Iaddend., having one or more conductive shields extending overthe area of the or each well, and also having means for causing the oreach shield potential to track the potential of the said one plate. 15.A voltage storage circuit as claimed in claim . .12.!. .Iadd.2.Iaddend.,wherein the said amplifier element is made up of first and secondsubstantially identical circuit portions, the first portion includingthe said input device and the said active follower means and the secondportion including the said current source, and wherein the said firstportion of the amplifier element is located within the said one or morewells, and the said second portion of the amplifier element is formedwithin one or more further wells, each of the conductivity type oppositeto that of the surrounding areas of the substrate, the or each furtherwell potential being substantially fixed in relation to the potential ofa supply line of the circuit.
 16. A voltage storage circuit . .asclaimed in claim 6, further including.!. .Iadd.comprising:an electronicinput switch element, operative in dependence upon the potential at aswitching electrode thereof; a storage capacitor, one plate of which isconnected to an input terminal of the circuit by way of said electronicinput switch element and the other plate of which is connected to acommon terminal of the circuit, to store an input signal being appliedbetween said input and common terminals when the circuit is in use;switch driving means connected to cause the switching electrodepotential to track the input terminal potential when the element is inits ON condition, thereby maintaining the switching electrode potentialsubstantially fixed in relation to the input terminal potential, andoperable to cause the switching electrode to change, relative to theinput terminal potential, such that the element is changed from its ONcondition to its OFF condition; an amplifier element, having an inputconnected to said one plate and an output connected to an outputterminal of the circuit, for providing an output signal, between saidoutput and common terminals, dependent upon the voltage stored in saidstorage capacitor, which amplifier element includes an electronic inputdevice having a controllable current path provided between respectivefirst and second current-path electrodes of the electronic input deviceand also having a control electrode to which a potential is applied tocontrol the magnitude of current in said controllable current path, saidcontrol electrode being connected to said one plate, and said first andsecond current-path electrodes being connected with a potential trackingdevice such that both the first current-path electrode potential and thesecond current-path electrode potential track the control electrodepotential, whilst current flows in said controllable current path, sothat the respective potentials of the first and second current-pathelectrodes are kept substantially fixed in relation to the potential ofsaid one plate; and .Iaddend. input potential maintaining means,interposed between the said input terminal and the input side of thesaid input switch element, for maintaining the input-side potential ofthe input switch element, after the element is changed to the OFFcondition, substantially fixed in relation to the potential of the saidone plate of the storage capacitor.
 7. A voltage storage circuit asclaimed in claim 16, wherein the said input potential maintaining meanscomprise a further switch element connected in series with the saidinput switch element and operable, after the said input switch elementhas been changed to the OFF condition, to isolate the input side of thatelement from the said input terminal.
 18. A voltage storage circuit asclaimed in claim 17, wherein the said input potential maintaining meansfurther comprise an auxiliary capacitor connected between the input sideof the said input switch element and the said other plate of the saidstorage capacitor.
 19. A voltage storage circuit as claimed in claim 17,wherein the said input potential maintaining means further comprise afeedback switch element connected between the said amplifier element andthe input side of the said input switch element and operable, while theinput side of that element is so isolated, to apply thereto a potentialderived from the potential of the said one plate of the storagecapacitor.
 20. A voltage storage circuit as claimed in claim 1, whereinthe said amplifier element has a gain of substantially unity. 21.Voltage summation circuitry comprising:first, second and third inputnodes to which first, second and third potentials are respectivelyapplied when the circuitry is in use; a voltage storage circuitincluding:a storage capacitor, one plate of which is connected to aninput terminal of the circuit by way of an input switch element and theother plate of which is connected to a common terminal of the circuit.., to store an input signal being applied between said input and commonterminals when the circuit is in use.!.; and . .an.!. .Iadd.a unity-gain.Iaddend.amplifier element, having an input connected to said one plateand an output connected to an output terminal of the circuit, . .forproviding an output signal, between said output and common terminals,dependent upon the voltage stored in said storage capacitor.!..Iadd.such that the output terminal potential is substantially equal tothe potential of said one plate when the circuit is in use.Iaddend.,which amplifier element includes an electronic input device having acontrollable current path provided between respective first and secondcurrent-path electrodes of the electronic input device and also having acontrol electrode to which a potential is applied to control themagnitude of current in said controllable current path, said controlelectrode being connected to said one plate, and said first and secondcurrent-path electrodes being connected with a potential tracking devicesuch that both the first current-path electrode potential and the secondcurrent-path electrode potential track the control electrode potential,whilst current flows in said controllable current path, so that therespective potentials of the first and second current-path electrodesare kept substantially fixed in relation to the potential of said oneplate. ., said amplifier element having a gain of substantiallyunity.!.; an output node connected with the output terminal of thevoltage storage circuit; and switching means connected with said inputnodes and with said voltage storage circuit and switchable, after theinput switch element of the voltage storage circuit has been changed tothe OFF condition, from an input configuration to an outputconfiguration, said input configuration serving to connect said firstand second input nodes to said input and common terminals respectivelyof the voltage storage circuit, thereby to permit storage of thepotential difference between said first and second potentials in thestorage capacitor of the voltage storage circuit, and said outputconfiguration serving to connect the common terminal of the voltagestorage circuit to the third input node, thereby to produce at saidoutput node an output potential which is substantially equal to the sumof the third potential and the stored difference between the first andsecond potentials.
 22. Voltage summation circuitry comprising:first,second, third, fourth, fifth and sixth input nodes, a first pair ofinput voltages being applied to said first and second input nodes, asecond pair of input voltages being applied to said third and fourthinput nodes, and a third pair of input voltages being applied to saidfifth and sixth input nodes, when the circuitry is in use; first andsecond voltage storage circuits, each of said first and second voltagestorage circuits including:a storage capacitor, one plate of which isconnected to an input terminal of the circuit by way of an input switchelement and the other plate of which is connected to a common terminalof the circuit. ., to store an input signal being applied between saidinput and common terminals when the circuit is in use.!.; and . .an.!..Iadd.a unity-gain .Iaddend.amplifier element, having an input connectedto said one plate and an output connected to an output terminal of thecircuit, . .for providing an output signal, between said output andcommon terminals, dependent upon the voltage stored in said storagecapacitor.!. .Iadd.such that the output terminal potential issubstantially equal to the potential of said one plate when the circuitis in use.Iaddend., which amplifier element includes an electronic inputdevice having a controllable current path provided between respectivefirst and second current-path electrodes of the electronic input deviceand also having a control electrode to which a potential is applied tocontrol the magnitude of current in said controllable current path, saidcontrol electrode being connected to said one plate, and said first andsecond current-path electrodes being connected with a potential trackingdevice such that both the first current-path electrode potential and thesecond current-path electrode potential track the control electrodepotential, whilst current flows in said controllable current path, sothat the respective potentials of the first and second current-pathelectrodes are kept substantially fixed in relation to the potential ofsaid one plate. ., said amplifier element having a gain of substantiallyunity.!.; first and second output nodes connected with the respectiveoutput terminals of said first and second voltage storage circuits; andswitching means connected with said input nodes and with said voltagestorage circuits and switchable, after the respective input switchelements of the first and second voltage storage circuits have beenchanged to the OFF condition, from an input configuration to an outputconfiguration, said input configuration serving to connect said firstand second input nodes to said input and common terminals respectivelyof said first voltage storage circuit, and also to connect said thirdand fourth input nodes to said input and common terminals respectivelyof said second voltage storage circuit, thereby to permit storage, insaid storage capacitor of the first voltage storage circuit, of a firstpotential difference between the two input voltages of said first pairand to permit storage, in said storage capacitor of the second voltagestorage circuit, of a second potential difference between the two inputvoltages of said second pair, and said output configuration serving toconnect the respective common terminals of the first and second voltagestorage circuits to the fifth and sixth input nodes respectively,thereby to produce between said first and second output nodes a . .pairof output voltages the.!. potential difference . .between.!. which issubstantially equal to the sum of the potential difference between thetwo input voltages of said third pair and the difference between thestored first and second potential differences.
 23. Voltage doublingcircuitry comprising:first and second input nodes between which an inputvoltage to be doubled is applied when the circuitry is in use; first andsecond voltage storage circuits, each of said first and second voltagestorage circuits including:a storage capacitor, one plate of which isconnected to an input terminal of the circuit by way of an input switchelement and the other plate of which is connected to a common terminalof the circuit. ., to store an input signal being applied between saidinput and common terminals when the circuit is in use.!.; and . .an.!..Iadd.a unity-gain .Iaddend.amplifier element, having an input connectedto said one plate and an output connected to an output terminal of thecircuit, . .for providing an output signal, between said output andcommon terminals, dependent upon the voltage stored in said storagecapacitor.!. .Iadd.such that the output terminal potential issubstantially equal to the potential of said one plate when the circuitis in use.Iaddend., which amplifier element includes an electronic inputdevice having a controllable current path provided between respectivefirst and second current-path electrodes of the electronic input deviceand also having a control electrode to which a potential is applied tocontrol the magnitude of current in said controllable current path, saidcontrol electrode being connected to said one plate, and said first andsecond current-path electrodes being connected with a potential trackingdevice such that both the first current-path electrode potential and thesecond current-path electrode potential track the. .,.!. controlelectrode potential, whilst current flows in said controllable currentpath, so that the respective potentials of the first and secondcurrent-path electrodes are kept substantially fixed in relation to thepotential of said one plate. ., said amplifier element having a gain ofsubstantially unity.!.; first and second output nodes connectedrespectively with the respective output terminals of the first andsecond voltage storage circuits; and switching means connected with saidinput nodes and with said voltage storage circuits and switchable, afterthe respective input switch elements of the first and second voltagestorage circuits have been changed to the OFF condition, from an inputconfiguration to an output configuration, said input configurationserving to connect said first input node to both said input terminal ofsaid first voltage storage circuit and said common terminal of saidsecond voltage storage circuit, and also to connect said second inputnode to both said input terminal of said second voltage storage circuitand said common terminal of said first voltage storage circuit, therebyto cause each of the respective storage capacitors of said voltagestorage circuits to be charged to said input voltage, and said outputconfiguration serving to connect the respective common terminals of thefirst and second voltage storage circuits together so that said storagecapacitors are connected in series with one another between .Iadd.therespective amplifier-element inputs of .Iaddend.said first and second ..output nodes.!. .Iadd.voltage storage circuits, .Iaddend.thereby toproduce between . .those.!. .Iadd.said first and second .Iaddend.outputnodes an output voltage which is substantially double said inputvoltage.
 24. A voltage conversion stage comprising:voltage doublingcircuitry including:first and second input nodes between which an inputvoltage to be doubled is applied when the circuitry is in use; first andsecond voltage storage circuits, each of said first and second voltagestorage circuits including:a storage capacitor, one plate of which isconnected to an input terminal of the circuit by way of an input switchelement and the other plate of which is connected to a common terminalof the circuit. ., to store an input signal being applied between saidinput and common terminals when the circuit is in use.!.; and . .an.!..Iadd.a unity-gain .Iaddend.amplifier element, having an input connectedto said one plate and an output connected to an output terminal of thecircuit, . .for providing an output signal, between said output andcommon terminals, dependent upon the voltage stored in said storagecapacitor.!. .Iadd.such that the output terminal potential issubstantially equal to the potential of said one plate when the circuitis in use.Iaddend., which amplifier element includes an electronic inputdevice having a controllable current path provided between respectivefirst and second current-path electrodes of the electronic input deviceand also having a control electrode to which a potential is applied tocontrol the magnitude of current in said controllable current path, saidcontrol electrode being connected to said one plate, and said first andsecond current-path electrodes being connected with a potential trackingdevice such that both the first current-path electrode potential and thesecond current-path electrode potential track the control electrodepotential, whilst current flows in said controllable current path, sothat the respective potentials of the first and second current-pathelectrodes are kept substantially fixed in relation to the potential ofsaid one plate. ., said amplifier element having a gain of substantiallyunity.!.; first and second output nodes connected respectively with therespective output terminals of the first and second voltage storagecircuits; and switching means connected with said input nodes and withsaid voltage storage circuits and switchable, after the respective inputswitch elements of the first and second voltage storage circuits havebeen changed to the OFF condition, from an input configuration to anoutput configuration, said input configuration serving to connect saidfirst input node to both said input terminal of said first voltagestorage circuit and said common terminal of said second voltage storagecircuit, and also to connect said second input node to both said inputterminal of said second voltage storage circuit and said common terminalof said first voltage storage circuit, thereby to cause each of therespective storage capacitors of said voltage storage circuits to becharged to said input voltage, and said output configuration serving toconnect the respective common terminals of the first and second voltagestorage circuits together so that said storage capacitors are connectedin series with one another between .Iadd.the respective amplifierelement inputs of .Iaddend.said first and second . .output nodes.!..Iadd.voltage storage circuits.Iaddend., thereby to produce between ..those.!. .Iadd.said first and second .Iaddend.output nodes an outputvoltage which is substantially double said input voltage; comparatormeans connected for receiving a working voltage equal to or derived fromsaid input voltage and also connected for receiving a comparisonpotential and operable to perform a comparison between that workingvoltage and said comparison potential and to provide digital dataindicative of the result of the comparison; and voltage adjustment meansconnected between the respective common terminals of said first andsecond voltage storage circuits and operable, after said switching meanshave been switched from said input configuration to said outputconfiguration, to apply between those terminals an offset voltage havinga value selected, by said digital data, from a plurality of presetpossible values, thereby to produce between said output nodes ananalogue conversion voltage which differs from double said input voltageby the selected offset voltage.
 25. A voltage conversion stage asclaimed in claim 24, wherein the said comparator means perform the saidcomparison whilst the switching means of the voltage storage circuitsare in the said input configuration.
 26. A voltage conversion stage asclaimed in claim 24, wherein the said comparator means are connected tothe said first and second input nodes, so that the said input voltage isthe said working voltage, and provide first such digital data if thesaid input voltage is less than or equal to minus the said comparisonpotential, and provide second such digital data if the said comparisonpotential is less than or equal to the said input voltage, and providethird such digital data in all other cases, and wherein the offsetvoltage selected by the said second digital data is -V_(ref), where+V_(ref) is the offset voltage selected by the said first digital data,and the offset voltage selected by the said third digital data is zero;the said comparison potential being substantially equal to V_(ref) /4.27. An analogue-to-digital converter comprising:a series of N stages,each of said N stages being a voltage conversion stage including:voltagedoubling circuitry including:first and second input nodes between whichan input voltage to be doubled is applied when the circuitry is in use;first and second voltage storage circuits each of said first and secondvoltage storage circuits including:a storage capacitor, one plate ofwhich is connected to an input terminal of the circuit by way of aninput switch element and the other plate of which is connected to acommon terminal of the circuit. ., to store an input signal beingapplied between said input and common terminals when the circuit is inuse.!.; and . .an.!. .Iadd.a unity-gain .Iaddend.amplifier element,having an input connected to said one plate and an output connected toan output terminal of the circuit, . .for providing an output signal,between said output and common terminals, dependent upon the voltagestored in said storage capacitor.!. .Iadd.such that the output terminalpotential is substantially equal to the potential of said one plate whenthe circuit is use.Iaddend., which amplifier element includes anelectronic input device having a controllable current path providedbetween respective first and second current-path electrodes of theelectronic input device and also having a control electrode to which apotential is applied to control the magnitude of current in saidcontrollable current path, said control electrode being connected tosaid one plate, and said first and second current-path electrodes beingconnected with a potential tracking device such that both the firstcurrent-path electrode potential and the second current-path electrodepotential track the control electrode potential, whilst current flows insaid controllable current path, so that the respective potentials of thefirst and second current-path electrodes are kept substantially fixed inrelation to the potential of said one plate. ., said amplifier elementhaving a gain of substantially unity.!.; first and second output nodesconnected respectively with the respective output terminals of the firstand second voltage storage circuits; and switching means connected withsaid input nodes and with said voltage storage circuits and switchable,after the respective input switch elements of the first and secondvoltage storage circuits have been changed to the OFF condition, from aninput configuration to an output configuration, said input configurationserving to connect said first input node to both said input terminal ofsaid first voltage storage circuit and said common terminal of saidsecond voltage storage circuit, and also to connect said second inputnode to both said input terminal of said second voltage storage circuitand said common terminal of said first voltage storage circuit, therebyto cause each of the respective storage capacitors of said voltagestorage circuits to be charged to said input voltage, and said outputconfiguration serving to connect the respective common terminals of thefirst and second voltage storage circuits together so that said storagecapacitors are connected in series with one another between .Iadd.therespective amplifier element inputs of .Iaddend.said first and second ..output nodes.!. .Iadd.voltage storage circuits.Iaddend., thereby toproduce between . .those.!. .Iadd.said first and second .Iaddend.outputnodes an output voltage which is substantially double said inputvoltage; comparator means connected for receiving a working voltageequal to or derived from said input voltage and also connected forreceiving a comparison potential and operable to perform a comparisonbetween that working voltage and said comparison potential and toprovide digital data indicative of the result of the comparison; andvoltage adjustment means connected between the respective commonterminals of said first and second voltage storage circuits andoperable, after said switching means have been switched from said inputconfiguration to said output configuration, to apply between thoseterminals an offset voltage having a value selected, by said digitaldata, from a plurality of preset possible values, thereby to producebetween said output nodes an analogue conversion voltage which differsfrom double said input voltage by the selected offset voltage, ananalogue voltage to be digitised being applied between said first andsecond input nodes of the first stage of the series, and said first andsecond input nodes of each successive stage being connected to saidfirst and second output nodes respectively of the immediately-precedingstage; control means operable to cause the switching means of each ofsaid stages in succession to be switched from said input configurationto said output configuration, such switching being controlled to occurin each of the stages, except for the first stage, at a time when theswitching means of the immediately-preceding stage is in the outputconfiguration so that prior to such switching the stage being switchedreceives as its input voltage the analogue conversion voltage producedby that immediately-preceding stage and so produces its analogueconversion voltage in dependence thereupon after such switching; anddata processing means connected for receiving the said digital dataprovided by said N stages and operative to derive therefrom a digitaloutput word, comprising N+1 bits, representative of the applied analoguevoltage.
 28. An analogue-to-digital converter as claimed in claim 27,operative alternately in first and second clock phases, wherein the saidcontrol means operate in the said first clock phase to maintain therespective switching means of the odd-numbered stages of the series inthe input configuration whilst maintaining the respective switchingmeans of the even-numbered stages in the said output configuration butoperate in the said second clock phase to maintain the respectiveswitching means of the even-numbered stages in the said inputconfiguration whilst maintaining the respective switching means of theodd-numbered stages in the output configuration.
 29. Ananalogue-to-digital converter as claimed in claim 27, wherein for atleast one pair of adjacent stages of the series, the respective storagecapacitors of the said first and second voltage storage circuits in thesecond stage of the pair are smaller in capacitance than the comparablestorage capacitors in the first stage of the pair.
 30. Ananalogue-to-digital converter as claimed in claim 29, wherein thestorage capacitance ratio of the two stages of one or each such pair isapproximately 2:1.
 31. An analogue-to-digital converter as claimed inclaim 27, wherein for at least one pair of adjacent stages of theseries, the respective amplifier element input devices of the said firstand second voltage storage circuits in the second stage of the pair aresmaller in width than the comparable input devices in the first stage ofthe pair.
 32. An analogue-to-digital converter as claimed in claim 31,wherein the input device width ratio of the two stages of one or eachsuch pair is approximately 2:1.
 33. An analogue-to-digital converter asclaimed in claim 27, wherein for at least one pair of adjacent stages ofthe series, the respective currents in the controllable current paths ofthe amplifier element input devices of the said first and second voltagestorage circuits in the second stage of the pair are smaller than thecomparable currents in the first stage of the pair.
 34. Ananalogue-to-digital converter as claimed in claim 33, wherein thecurrent ratio of the two stages of one or each such pair isapproximately 2:1. An analogue-to-digital converter as claimed in claim27, wherein in each of the second to nth stages of the converter, where2≦n≦N, each of the respective storage capacitors of the said first andsecond voltage storage circuits of the stage has a capacitance that isreduced, relative to the capacitance of the comparable storage capacitorof the immediately-preceding stage, by a first scaling factor that isconstant throughout those second to nth stages.
 36. Ananalogue-to-digital converter as claimed in claim 35, wherein the saidfirst scaling factor is approximately
 2. 37. An analogue-to-digitalconverter as claimed in claim 27, wherein in each of the second to nthstages of the converter, where 2≦n≦N, the amplifier element input deviceof each voltage storage circuit of the stage is of a channel width thatis reduced, relative to the channel width of the comparable amplifierelement input device of the immediately-preceding stage, by a secondscaling factor that is constant throughout those second to nth stages.38. An analogue-to-digital converter as claimed in claim 37, wherein thesaid second scaling factor is approximately
 2. 39. Ananalogue-to-digital converter as claimed in claim 27, wherein in each ofthe second to nth stages of the converter, where 2≦n≦N, the current ineach of the said controllable current paths of the amplifier elementinput devices of the stage is controlled to be reduced, relative to thecurrent in the comparable controllable current path of theimmediately-preceding stage, by a third scaling factor that is constantthroughout those second to nth stages.
 40. An analogue-to-digitalconverter as claimed in claim 39, wherein the said third scaling factoris approximately
 2. 41. An analogue-to-digital converter as claimed inclaim 27, wherein, for at least one pair of adjacent stages of theseries, at least one of the said preset possible values of the offsetvoltage in the second stage of the pair is adjusted fractionally ascompared with the corresponding preset possible value of the offsetvoltage in the first stage of the pair.
 42. An analogue-to-digitalconverter as claimed in claim 27, wherein the said data processing meansare operable to fractionally adjust the digital data provided by therespective comparator means of successive stages of the series so as tofacilitate correction of voltage conversion errors in those successivestages.
 43. An analogue-to-digital converter comprising:first and secondstages, each of said stages being a voltage conversion stageincluding:voltage doubling circuitry including:first and second inputnodes between which an input voltage to be doubled is applied when thecircuitry is in use; first and second voltage storage circuits, each ofsaid first and second voltage storage circuits including:a storagecapacitor, one plate of which is connected to an input terminal of thecircuit by way of an input switch element and the other plate of whichis connected to a common terminal of the circuit. ., to store an inputsignal being applied between said input and common terminals when thecircuit is in use.!.; and . .an.!. .Iadd.a unity-gain .Iaddend.amplifierelement, having an input connected to said one plate and an outputconnected to an output terminal of the circuit, . .for providing anoutput signal, between said output and common terminals, dependent uponthe voltage stored in said storage capacitor.!. .Iadd.such that theoutput terminal potential is substantially equal to the potential ofsaid one plate when the circuit is in use.Iaddend., which amplifierelement includes an electronic input device having a controllablecurrent path provided between respective first and second current-pathelectrodes of the electronic input device and also having a controlelectrode to which a potential is applied to control the magnitude ofcurrent in said controllable current path, said control electrode beingconnected to said one plate, and said first and second current-pathelectrodes being connected with a potential tracking device such thatboth the first current-path electrode potential and the secondcurrent-path electrode potential track the control electrode potential,whilst current flows in said controllable current path, so that therespective potentials of the first and second current-path electrodesare kept substantially fixed in relation to the potential of said oneplate. ., said amplifier element having a gain of substantiallyunity.!.; first and second output nodes connected respectively with therespective output terminals of the first and second voltage storagecircuits; and switching means connected with said input nodes and withsaid voltage storage circuits and switchable, after the respective inputswitch elements of the first and second voltage storage circuits havebeen changed to the OFF condition, from an input configuration to anoutput configuration, said input configuration serving to connect saidfirst input node to both said input terminal of said first voltagestorage circuit and said common terminal of said second voltage storagecircuit, and also to connect said second input node to both said inputterminal of said second voltage storage circuit and said common terminalof said first voltage storage circuit, thereby to cause each of therespective storage capacitors of said voltage storage circuits to becharged to said input voltage, and said output configuration serving toconnect the respective common terminals of the first and second voltagestorage circuits together so that said storage capacitors are connectedin series with one another between .Iadd.the respective amplifierelement inputs of .Iaddend.said first and second . .output nodes.!..Iadd.voltage storage circuits.Iaddend., thereby to produce between ..those.!. .Iadd.said first and second .Iaddend.output nodes an outputvoltage which is substantially double said input voltage; comparatormeans connected for receiving a working voltage equal to or derived fromsaid input voltage and also connected for receiving a comparisonpotential and operable to perform a comparison between that workingvoltage and said comparison potential and to provide digital dataindicative of the result of the comparison; and voltage adjustment meansconnected between the respective common terminals of said first andsecond voltage storage circuits and operable, after said switching meanshave been switched from said input configuration to said outputconfiguration, to apply between those terminals an offset voltage havinga value selected, by said digital data, from a plurality of presetpossible values, thereby to produce between said output nodes ananalogue conversion voltage which differs from double said input voltageby the selected offset voltage, said first and second stages .Iadd.being.Iaddend.connected together such that said first and second output nodesof the first stage are connected to said first and second input nodesrespectively of the second stage and said first and second output nodesof said second stage are connected to said first and second input nodesrespectively of the first . .such.!. stage, an analogue voltage to bedigitised being applied, at the start of an iterative conversionoperation of the converter, between said first and second input nodes ofsaid first stage; control means operable to cause the switching means ofthe first and second stages to be switched alternately, starting withthe first stage, from said input configuration to said outputconfiguration, such switching being controlled to occur in one stage ata time when the switching means of the other stage are in the outputconfiguration so that prior to such switching the one stage beingswitched receives as its input voltage the analogue conversion voltageproduced by the other stage and so produces its analogue conversionvoltage in dependence thereupon after such switching; and dataprocessing means connected for receiving said digital data providedalternately by the first and second stages during the course of saiditerative conversion operation and operative to derive therefrom adigital output word representative of the applied analogue voltage. 44.An analogue-to-digital converter, operable alternately in first andsecond clock phases, including:first and second input nodes betweenwhich an analogue input voltage to be digitised can be applied when theconverter is in use; first and second voltage storage circuits, eachincluding respective first and second storage capacitors and aunity-gain amplifier element having respective input and outputterminals, which element includes an electronic input device having acontrollable current path provided between respective first and secondcurrent-path electrodes of the device and also having a controlelectrode to which a potential is applied to control the magnitude ofcurrent in the said current path, the said control electrode beingconnected to the said input terminal of the amplifier element, and thesaid first and second current-path electrodes being connected with apotential tracking device such that both the first current-pathelectrode potential and the second current-path electrode potentialtrack the control electrode potential, whilst current flows in the saidcontrollable current path, so that the respective potentials of thefirst and second current-path electrodes are kept substantially fixed inrelation to the potential of the said input terminal; input samplingmeans operable during an initial one of the clock phases to connect thesaid input terminal of the first voltage storage circuit to the saidfirst input node and to connect the said input terminal of the secondvoltage storage circuit to the said second input node; first and secondoutput nodes connected respectively with the amplifier element outputterminals of the said first and second voltage storage circuits;comparator means connected to the said first and second output nodes andalso connected for receiving a comparison potential and operable in eachclock phase to perform a comparison between the potential differencebetween the first and second output nodes and the said comparisonpotential and to provide digital data indicative of the result of thecomparison; voltage adjustment means having a pair of connectionterminals and operable in each clock phase to apply between thoseterminals an offset voltage having a value selected, by the said digitaldata provided by the said comparator means in the immediately-precedingclock phase, from a plurality of preset possible values; switching meansoperable in the first clock phase to connect the two first storagecapacitors and the said connection terminals in series between therespective input terminals of the amplifier elements, whilst connectingthe said second storage capacitors in parallel with one another betweenthe first and second output nodes, and operable in the second clockphase to connect the two second storage capacitors and the saidconnection terminals in series between the respective input terminals ofthe amplifier elements, whilst connecting the said first storagecapacitors in parallel with one another between the first and secondoutput nodes; and data processing means connected for receiving the saiddigital data provided by the said comparator means over a predeterminednumber of the said clock phases and operative to derive therefrom adigital output word representative of the applied analogue inputvoltage.
 45. An analogue-to-digital converter including a plurality ofmutually-similar voltage conversion stages connected in series so thatthe output of one stage provides an input to the next stage, each stageincluding a storage capacitor selectively connectible to the input ofthe stage for storing an input voltage of the stage and also includingan amplifier element .Iadd.connected or .Iaddend.selectively connectiblebetween the storage capacitor and the output of the stage for deliveringan output voltage of the stage which is dependent on the stored inputvoltage, wherein in at least one stage, other than the first stage, ofthe series the storage capacitor capacitance is smaller than the storagecapacitor capacitance of the immediately-preceding stage and/or thewidth of an input transistor of the amplifier element is smaller thanthe width of the input transistor of the amplifier element of theimmediately-preceding stage. .Iadd.46. A voltage storage circuit asclaimed in claim 16, wherein the potential tracking device includes acurrent source, connected to the said first current-path electrode forcausing the first current-path electrode potential to track the controlelectrode potential, and active follower means connected operativelybetween the said first and second current-path electrodes for causingthe second current-path electrode potential to track the firstcurrent-path electrode potential. .Iaddend..Iadd.47. A voltage storagecircuit as claimed in claim 46, wherein the said electronic input deviceis an FET input transistor and the said control electrode is the gateelectrode of the FET input transistor, the first current-path electrodeis the source electrode of the FET input transistor, the said secondcurrent-path electrode is the drain electrode of the FET inputtransistor, and the said controllable current path is provided by thedrain-source channel of the FET input transistor. .Iaddend..Iadd.48. Avoltage storage circuit as claimed in claim 47, wherein the said activefollower means comprise a cascoding FET transistor connected with itsdrain-source channel in series with the drain-source channel of the saidFET input transistor so that the source electrode potential of thecascoding transistor tracks the gate electrode potential thereof andalso comprise a bias generator connected operatively between the sourceelectrode of the FET input transistor and the gate electrode of thecascoding transistor for maintaining therebetween a substantiallyconstant potential difference. .Iaddend..Iadd.49. A voltage storagecircuit as claimed in claim 46, wherein the said amplifier element ismade up of first and second substantially identical circuit portions,the first portion including the said input device and the said activefollower means and the second portion including the said current source..Iaddend..Iadd.50. A voltage storage circuit as claimed in claim 16,wherein the said switching electrode potential is derived from the saidoutput signal. .Iaddend..Iadd.51. A voltage storage circuit as claimedin claim 50, wherein the said switch driving means are connectedoperatively with the said output terminal and are operable, independence upon a switching signal received thereby, to apply to thesaid switching electrode either an ON potential, for maintaining thesaid input switch element in its ON condition, or an OFF potential, formaintaining the said input switch element in its OFF condition, the saidON and OFF potentials being each substantially fixed in relation to thesaid output terminal potential but differing from one another by apredetermined amount. .Iaddend..Iadd.52. A voltage storage circuit asclaimed in claim 51, having respective first and second biassing linesconnected operatively to the said output terminal so as to be atpotentials that are respectively fixed in relation to the outputterminal potential, the second biassing line potential being equal toone of the said ON and OFF potentials and the potential differencebetween the said first and second biassing lines being greater than orequal to the said predetermined amount, wherein the said switch drivingmeans include a bootstrap capacitor one plate of which is connected tothe said switching electrode for providing the said switching electrodepotential and also include connecting means connected with both platesof the bootstrap capacitor and with the said biassing lines andswitchable, when the switching electrode potential is to be changed fromthe said one of its ON and OFF potentials to the other of thosepotentials, from a charging configuration, serving to connect the saidone plate of the bootstrap capacitor to the said second biassing linewhilst connecting the other plate thereof to the said first biassingline, to a floating configuration serving to isolate the said one platefrom the second biassing line whilst connecting the said other plate tothe said second biassing line, thereby to cause the potential at thesaid one plate to be changed from the second biassing line potential toa potential differing therefrom by the said predetermined amount..Iaddend..Iadd.53. A voltage storage circuit as claimed in claim 51,having respective first, second and third biassing lines connectedoperatively to the said output terminal so as to be at potentials thatare respectively fixed in relation to the output terminal potential, thethird biassing line potential being equal to one of the said ON and OFFpotentials and the potential difference between the said first andsecond biassing lines being greater than or equal to the saidpredetermined amount, wherein the said switch driving means include abootstrap capacitor one plate of which is connected to the saidswitching electrode for providing the said switching electrode potentialand also include connecting means connected with both plates of thebootstrap capacitor and with the said biassing lines and switchable,when the switching electrode potential is to be changed from the saidone of its ON and OFF potentials to the other of those potentials, froma charging configuration, serving to connect the said one plate of thebootstrap capacitor to the said third biassing line whilst connectingthe other plate thereof to the said first biassing line, to a floatingconfiguration serving to isolate the said one plate from the thirdbiassing line whilst connecting the said other plate to the said secondbiassing line, thereby to cause the potential at the said one plate tobe changed from the third biassing line potential to a potentialdiffering therefrom by the said predetermined amount. .Iaddend..Iadd.54.A voltage storage circuit as claimed in claim 51, wherein the saidelectronic input switch element is a MOSFET transistor and one of thesaid ON and OFF potentials is substantially the same as the said outputterminal potential. .Iaddend..Iadd.55. A voltage storage circuit asclaimed in claim 16, wherein the said amplifier element has a gain ofsubstantially unity. .Iaddend..Iadd.56. An analogue-to-digital converteras claimed in claim 45, having N such stages, wherein in each of thesecond to nth stages of the converter, where 2≦n≦N, the storagecapacitor of the stage has a capacitance that is reduced, relative tothe capacitance of the comparable storage capacitor of theimmediately-preceding stage, by a first scaling factor that is constantthroughout those second to nth stages. .Iaddend..Iadd.57. Ananalogue-to-digital converter as claimed in claim 56, wherein thevoltage gain of each stage is 2 and said first scaling factor isapproximately
 2. .Iaddend..Iadd.58. An analogue-to-digital converter asclaimed in claim 45, having N such stages, wherein in each of the secondto nth stages of the converter, where 2≦n≦N, the amplifier element inputtransistor of the stage is of a channel width that is reduced, relativeto the channel width of the comparable amplifier element inputtransistor of the immediately-preceding stage, by a second scalingfactor that is constant throughout those second to nth stages..Iaddend..Iadd.59. An analogue-to-digital converter as claimed in claim58, wherein the voltage gain of each stage is 2 and said second scalingfactor is approximately
 2. .Iaddend..Iadd.60. An analogue-to-digitalconverter as claimed in claim 45, wherein said amplifier element of eachstage has current control means connected to said input transistor forcausing a controlled working current to flow therethrough when theconverter is in use, the current control means being such that themagnitude of the controlled working current for said one stage issmaller than that for the immediately-preceding stage of the series..Iaddend..Iadd.61. An analogue-to-digital converter as claimed in claim60, having N such stages, wherein in each of the second to nth stages ofthe converter, where 2≦n≦N, said controlled working current for thestage is reduced, relative to said controlled working current in theimmediately-preceding stage, by a third scaling factor that is constantthroughout those second to nth stages. .Iaddend..Iadd.62. Ananalogue-to-digital converter as claimed in claim 61, wherein thevoltage gain of each stage is 2 and said third scaling factor isapproximately
 2. .Iaddend..Iadd.63. An analogue-to-digital converter asclaimed in claim 45, wherein each stage includes:comparator meansoperable to compare said input voltage of the stage with a predeterminedcomparison potential and to produce a digital data signal having a firstvalue if the result of the comparison is that the input voltage isgreater than or equal to the comparison potential, a second value if theresult of the comparison is that the input voltage is less than minusthe comparison potential, and a third value in all other cases; andconversion voltage generating means, connected to said comparator meansfor receiving therefrom said digital data signal produced thereby, andincluding said storage capacitor and said amplifier element of thestage, for determining said output voltage of the stage in dependenceupon the value of the received digital data signal such that the outputvoltage is twice the input voltage less a predetermined referencepotential when the digital data signal has said first value, and istwice the input voltage plus said predetermined reference potential whenthe digital data signal has the second value, and is twice the inputvoltage when the digital data signal has the third value; the converterfurther comprising data processing means connected for receiving therespective digital data signals produced by the comparator means of thestages and operable to process those signals to produce a digital outputword representative of the input voltage of the first stage..Iaddend..Iadd.64. An analogue-to-digital converter as claimed in claim44, wherein: each said storage capacitor has a first plate which is theplate thereof that is connectable, by said switching means, to saidinput terminal of the amplifier element in the voltage storage circuitto which that storage capacitor belongs; and for each said voltagestorage circuit:a switch element of the input sampling means that isconnected to the amplifier element input terminal, and switch elementsof said switching means that are connected to said first plates of thestorage capacitors, are formed in one or more wells of the oppositeconductivity type to that of the surrounding material of a substrate inwhich the voltage storage circuit concerned is formed, there being meansfor causing the or each well potential to be substantially fixed inrelation to the output terminal potential of the amplifier element inthe voltage storage circuit concerned. .Iaddend..Iadd.65. Ananalogue-to-digital converter as claimed in claim 44, wherein said inputsampling means include, for each said voltage storage circuit: anelectronic input switch element, operative in dependence upon thepotential at a switching electrode thereof, the voltage storage circuitconcerned further including switch driving means connected to cause theswitching electrode potential to track the input terminal potential whenthe element is in its ON condition, thereby maintaining the switchingelectrode potential substantially fixed in relation to the inputterminal potential, and operable to cause the switching electrodepotential to change, relative to the input terminal potential, such thatthe element is changed from its ON condition to its OFF condition; andinput potential maintaining means, interposed between said inputterminal and the input side of said input switch element, formaintaining the input-side potential of said electronic input switchelement, after the element is changed to the OFF condition,substantially fixed in relation to the potential of said input terminal..Iaddend..Iadd.66. An analogue-to-digital converter as claimed in claim65, wherein said input potential maintaining means comprise, for eachvoltage storage circuit, a further switch element connected in serieswith said input switch element and operable, after said input switchelement has been changed to the OFF condition, to isolate the input sideof that element from said input terminal. .Iaddend..Iadd.67. Ananalogue-to-digital converter as claimed in claim 65, wherein said inputpotential maintaining means further comprise, for each voltage storagecircuit, a feedback switch element connected between said amplifierelement and the input side of said input switch element and operable,while the input side of that element is isolated, to apply thereto apotential derived from the potential of said input terminal. .Iaddend.